Activity
From 08/05/2025 to 09/03/2025
09/03/2025
- TC 01:23 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?
- Hello Maxim -
Just getting back to you on our plan for a reference project. The reference project that we will be putting together will be root port, and not endpoint. So I don't believe it will support your use case. We will continu...
09/02/2025
- MW 07:36 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?
- Hello Maxim,
You only need 1 100 MHz reference clock to run the PCIe transceiver blocks. You should be able to use either pair (G16/G17 or G12/G13), just make sure you specify the correct pins in the quartus project. Our design requ... - MF 02:08 PM FPGA Development: RE: Fail to program device
- As shown by the log file it appears that you do not have the ARM toolchain installed. It is failing to compile the bootloader code. Please follow this wiki to install the GCC-ARM-11.2 toolchain.
https://support.criticallink.com/redmin...
08/29/2025
- KM 08:36 PM PCB Development: RE: PCIe connection to Computer MB
- Hello,
yes, actually it is worse than that.. the FPGA can only tolerate about 10mA, and must be less than 1.2V during power up ... so best to add 100 ohm pull-down to both these signals.
thanks,
Keith.
- MW 06:50 PM PCB Development: RE: PCIe connection to Computer MB
- Hi Keith,
I don't think you can drive it in the FPGA (PCIe needs to be up fairly quickly and may need to be there before the FPGA fully configures).
I would just tie or (use on a 100 ohm as you suggest) both lines to ground and ens... - KM 12:36 AM PCB Development: RE: PCIe connection to Computer MB
- Hi,
Actually, there is another issue, in EP mode, the Presecence signals, PRSNT2_*X1*# and PRSNT2_*X4*# need to be pulled-down by the Target/EP device,
however, these signals are pulled-up on the SoM, for the PCIE_X4_PRSNT2n_3V3 si... - MK 06:25 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?
- Hello Tom,
Thanks for the explanation.
Me and Keith, we are working together. We've ordered a cable (PCIe edge on both ends and cross-connect - to make it possible to connect the Mity Carrier board as PCIe End-Point)
I saw also a ki... - MK 06:13 PM FPGA Development: RE: Fail to program device
- Mike, please see attached log of the compilation
- MK 06:07 PM FPGA Development: RE: Fail to program device
- Hello Mike,
No I didn't made any changes. I removed everything. I clone again, navigate to directory and run command "make jic". It run again and again no files as expected
08/28/2025
- MF 08:58 PM FPGA Development: RE: Fail to program device
- Did you make changes to the design to switch to FPGA first as described in my previous post? Or are you just trying to compile the reference design as is?
If you made changes to the design can you please list those changes and upload ... - MK 08:28 PM FPGA Development: RE: Fail to program device
- Hello Mike,
Thanks again for your help!!!
I've followed the instructions that you send me yesterday. The command "make jic" compiled the design.
I see directory software and under the path that specified in instructions, also in th... - MF 04:36 PM FPGA Development: RE: Fail to program device
- > But, since we are using FPGA ONLY (no HPS), should this instructions to be applied, or we can generate .jic only??
You'll have to change our reference design from HPS First to FPGA first. This can be done by removing the "HPS FIRST"... - MK 02:16 PM FPGA Development: RE: Fail to program device
- Hello Mike,
I'm going to follow the instructions.
But, since we are using FPGA ONLY (no HPS), should this instructions to be applied, or we can generate .jic only??
Also, I'm not sure about your comment regarding Programming GUI. Do... - TC 08:13 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?
- Hello Maxim,
We will coordinate this with Engineering Management and get back to you mid-next week. Since I know you are digging in right now, and I also believe we will not have it immediately, what is the timeframe for which this wo... - MK 02:06 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?
- Hello Mike,
Thanks for your help. I've got the attached reference.
I have a question: do you have any estimation for the PCIe reference? Does this going to be Root Host or also End Point?? We are going to implement End Point
Thanks,
... - MF 01:42 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?
- Maxim,
Attached is our reference design for 25.1. This is not formally released yet as we are still working on wrapping it up. However, the FPGA reference design part is primarily complete, it is the bootloader/Linux Kernel we are sti... - KM 03:23 PM PCB Development: RE: PCIe connection to Computer MB
- Hello,
Samtec does offer Cross-Over type of cable in their Gen 4 and Gen 5 cables.
https://www.samtec.com/products/pciec-g5
We should order one and try it out soon
thanks,
Keith.
- MW 09:45 AM PCB Development: RE: PCIe connection to Computer MB
- Hi Keith,
Your concern is valid. You will need some sort of "cross-over" cable to swap Tx/Rx lines, etc.
I am looking around, I thought maybe Samtec might have something you could use.
Our Standard A5 SOM (larger, coming out in...
08/27/2025
- MF 09:18 PM FPGA Development: RE: Fail to program device
- Maxim,
Please use the instructions found here for programming the QSPI NOR Flash (from the command line): https://support.criticallink.com/redmine/projects/mitysom_a5/wiki/Building_fpga_242pro
I have not found a way to get the Prog... - Hello
I've just got MitySOM_A5 Dev. Kit and started to work on it.
I'm trying to create my own project based on CriticalLink BASE Example Project (clone from GIT, PRO 24.2 Stable)
The idea is not to use HPS for this project, but FPGA ... - Hello,
I'm trying to create an example design for AXI MCDMA for PCIe. But this IP core is exist in Q25.x versions only.
All the Example Projects provided by CriticalLink are in older versions: Q23.4, Q24.1, Q24.2
Does anyone tried to... - KM 08:51 PM PCB Development: RE: PCIe connection to Computer MB
- however I think the Tx and Rx lines need to be swapped w.r.t. the connector between EP and RP ... we cannot change the direction of the GTS signals on the FPGA.
can you please confirm this point ?
- KM 08:20 PM PCB Development: RE: PCIe connection to Computer MB
- okay I see there are some 0 ohm resistors to feedback the REFCLK+/- (PCIe_CLK) in end point mode... R81 and R83 on carrier board...
is this all that is needed to make the connection into standard motherboard ?
- Hello,
We are working on testing the PCIe interface on the Mighty-Mini Agilex-5E dev kit.
The PCIe x4 connector is a socket (Root Port).
in order to connect this to a standard computer mother board, also RP root port, we are g... - MF 08:28 PM PCB Development: RE: FAN enable
- Keith,
The FAN_EN GPIO can be enabled by exporting the GPIO in sysfs and driving it high. - Hello,
Is there a Linux software command to enable the +5V Fan from the HPS ? or a register we can write to to enable the FAN ?
We see that the SOM PCBA gets relatively hot > +50C, and we do not want to over stress the development...