Activity
From 06/21/2026 to 07/20/2026
07/13/2026
- EH 01:13 PM FPGA Development: RE: Not being able to Make jic
- Good morning,
I have readded the PCIe RP IP, but it I still can't regenerate/update the a5e because the tool complaints about the hps emif.
Thank you,
Eleonora
07/10/2026
- MF 03:55 PM FPGA Development: RE: Not being able to Make jic
- I believe the PCIe RP IP needs to be regenerated / re-added if you switch between production silicon or R0 silicon so that may be your issue with the PCIe IP.
The speed grade 4 SOM is capable of 1066 MHz DDR while the speed grade 6 SB... - EH 03:36 PM FPGA Development: RE: Not being able to Make jic
- Yes,
The actual label on the SOM is A5ED-B64-144-SRC-X, but the box says A5ED-B64-144-SRI-X
I checked the SBC also using jtagconfig and it came back as
1) USB-BlasterII [USB-1]
4BA06477 ARM_CORESIGHT_SOC_600
0364F0DD A5E(C0... - MF 02:57 PM FPGA Development: RE: Not being able to Make jic
- Eleonora,
Can you read the label / sticker that is on the SOM module? I believe the device you actually have installed into the development kit is the *A5ED-B64-144-SRC-X* and not *A5ED-B64-144-SRI*. I think this is where the confusio... - EH 01:46 PM FPGA Development: RE: Not being able to Make jic
- It actually came back with different FPGA - the one that you have
jtagconfig
1) USB-BlasterII [USB-1]
4BA06477 ARM_CORESIGHT_SOC_600
0364F0DD A5E(C065BB32AR0|D065BB32AR0)
I'll change the devise and start over.
I'll let...
07/09/2026
- MF 09:21 PM FPGA Development: RE: Not being able to Make jic
- No the SD card is irrelevant at this stage. JTAG talks directly to the SoC device.
Have you confirmed the device you are trying to flash also has the matching ID via jtagconfig?
If you're still stuck, can you post the entire output... - EH 09:15 PM FPGA Development: RE: Not being able to Make jic
- I get the correct device
quartus_pfg -i output_files/a5e.hps.jic | grep "Device"
Device name: A5ED065BB32A
Device name: A5ED065BB32AI4S
Is it possible to be a SD card mismatch? A coworker of mine might have used a mitySBC FPGA wh... - MF 08:39 PM FPGA Development: RE: Not being able to Make jic
- Correction to my last statement, jtagconfig doesn't list the temperature / speed grade (because it is not a gating factor to flash the device).
So jtagconfig reported *A5ED065BB32AR0* while my device is really *A5ED065BB32AE6SR0* - MF 08:34 PM FPGA Development: RE: Not being able to Make jic
- Hi Eleonora,
Yes *A5ED065BB32AI4S* is the correct part number for *A5ED-B64-144-SRI* .
Please confirm the output JIC was compiled for the correct device by running the following:
*Note - The second string is the full string. I s... - EH 08:18 PM FPGA Development: RE: Not being able to Make jic
- Hello Mike,
Deleting the u-boot-socfpga and bootloade.stamp and running make jic did give me test/ folder and produced *.jic file. Unfortunately, when I tried to program through JTAG, using:
quartus_pgm -m jtag -o "piv;output_files/a5e...
07/08/2026
- MF 09:52 PM FPGA Development: RE: Not being able to Make jic
- Hi Eleonora,
The test/Kconfig error most likely means the U-Boot source tree under software/bootloader/u-boot-socfpga is incomplete. The first time you build, the project Makefile clones U-Boot from our git server into that directory ... - Hi,
I have the example design for PCIE Rootport. It was in a special folder for my use. I made some changes and I'm trying to run make jic, but it gets to place where it can't find test/Kconfig and errors out. I have looked into a mity...