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VDTo enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)

Added by Vasu Devunuri 10 days ago

We tried the following combinations for working with a FMC (https://docs.opsero.com/op063/datasheet/overview/)

  1. To PCIe Endpoints
    set_location_assignment PIN_BK31 -to fmc_ep_perst_n_0
    set_location_assignment PIN_BW28 -to fmc_ep_perst_n_1
    set_location_assignment PIN_BU109 -to mp2m_ep_perst_n_2
  1. To PCIe Rootports.4C(port 0) and 4B (port 1) PERSTn to check
    #set_location_assignment PIN_BM28 -to pin_perst_n
    set_location_assignment PIN_BF32 -to pin_perst_n
    #set_location_assignment PIN_BU31 -to pin_perst_n_1
    set_location_assignment PIN_BM28 -to pin_perst_n_1
    #5B bank for 1B (port 2) bank PERSTn
    set_location_assignment PIN_CF132 -to pin_perst_n_2

Replies (7)

VD RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals) - Added by Vasu Devunuri 10 days ago

To give more clarity on targeted banks:

4C Bank: pin_perst_n
4B Bank: pin_perst_n_1
1B Bank: pin_perst_n_2

MW RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals) - Added by Michael Williamson 10 days ago

Hello,

Is BK31 a PCIe reset capable pin?

The Carrier board design uses high speed bi-directional analog MUX to allow selecting between HVIO pins or HSIO pins for the LA pins on the FMC interface.

From the Carrier Schematic:

With the correct mux enablement.

FPGA pin BW28 can be connected to LA03_P of the FMC connector.
FPGA pin BM28 can be connected to LA03_N of the FMC connector.
FPGA pin BF32 can be connected to LA13_P of the FMC connector.
FPGA pin BU31 can be connected to LA03_P of the FMC connector.
FPGA pin BM28 can be connected to LA04_P of the FMC connector.
FPGA pin CF132 is connected to the PCIE Edge connector interface on the WAKE_N line (it is not routed to the FMC connector).

These may not be routed to where you need them for the adapter FMC card you have selected. We could not predict where to route the PCIe Reset fixed pins.

I will see about providing instructions to configure the mux, in general you can set the mux up using a device tree configuration with the GPIO pins.

For root port control / mode, it has been unclear how the current IP supplied by Altera drives the PCIe reset pin (it doesn't, neither does the example project on the github site). We have experimented adding logic at the top level to drive the reset pin on startup.

With regards,
Mike

VD RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals) - Added by Vasu Devunuri 10 days ago

Hi Mike,

For Rootport, we generally expect PERSTn for RP to come from FPGA IO driven by BMC on boards as shown below (just an example). So I am looking for logic on board that drives PCIe RP and EP PERSTn.

[cid:a5c32161-6e5b-4a3b-aed9-43515a47007f]
Regards,
Vasu
________________________

MW RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals) - Added by Michael Williamson 10 days ago

Hi Vasu,

The link or picture didn't show up. Can you try again or send it to me via email or link?

Thanks,
Mike

VD RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals) - Added by Vasu Devunuri 9 days ago

[cid:60c940d4-d068-4db2-bd2c-e29f71f55391]

Altera Confidential
________________________

DV RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals) - Added by Daniel Vincelette 8 days ago

Hi Vasu,

The picture still didn't come through. Can you attach it via the "Choose Files" button at the bottom of the post? Also what does BMC stand for when you say "we generally expect PERSTn for RP to come from FPGA IO driven by BMC on boards"?

Thank you,
Dan

VD RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals) - Added by Vasu Devunuri 8 days ago

Hi Dan,

I am on mobile right now so cant attach files. BMC is Board Management Controller which handles power sequence of board and also telemetry. In general it drives perstn to root port as well as endpoint.

Altera Confidential

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