Activity
From 05/28/2014 to 06/26/2014
06/26/2014
- BD 11:22 AM Software Development: RE: SSD on MityDSP-L138F
- Hannes,
As mentioned in the errata, they do not recommend the "reset" approach because they cannot guarantee that it will work in a reasonable amount of time.
If you are going to go down this path, I suggest you test this approach ... - JC 08:25 AM Software Development: RE: Where to download the document about Memory Map and Register Address of IO Board 80-000268RI-2C and OMAPL138F
- These are provided by TI. You can find them here: http://www.ti.com/product/OMAP-L138/technicaldocuments
You should start with the "OMAP-L138 C6000 DSP+ARM Processor (Rev. H)" Datasheet and the "OMAP-L138 C6000 DSP+ARM Processor Techn... - MW 08:16 AM Software Development: RE: Where to download the document about Memory Map and Register Address of IO Board 80-000268RI-2C and OMAPL138F
- The memory map of the OMAP-L138 can be found on TI's main "OMAP-L138 web page":http://www.ti.com/product/omap-l138 (see the datasheet and the technical reference manual).
Not sure if that is what you are looking for.
06/25/2014
- only some brief documents are found in wiki,
Where can I download the document about Memory Map and Register Address of the IO Board 80-000268RI-2C and OMAPL138F? - LY 04:02 PM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Hello,Mike
Thank you very much.
- MW 12:42 PM FPGA Development: RE: DSP to FPGA SPI Setup Question
- What is your target update rate? Continuous?
You might try first to rip out all of the overhead on the tcDspFpgaSpi.cpp code (there is LCK_pend()/LCK_post() for serialization control, etc) and boil it down to the register writes.
... - LY 11:32 AM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Hello,Mike
Thank you for your help.
I have attached two pic
----one is the SPI bits transfer rate(This is our desired speed),
----another one is the word to word transfer rate(This is slow. We want it can be fast,Could you give u... - MW 10:47 AM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Can you check with a scope at what the clock rate is on the SPI device, and the interword write delay? I just want to confirm they are getting 50 MHz clock rate.
It might be the EMIFA transfer, but we should confirm that the SPI de... - AB 10:39 AM FPGA Development: RE: DSP to FPGA SPI Setup Question
- Update and followup question from the customer:
We have made the SPI work, but transmitting the word to word is slow.(about 11 uSec to send a 24bit word).
This is the code we run in the DSP:
spi = new tcDspFpgaSpi((void *)my_bas... - MF 12:01 PM Software Development: RE: Interrupting the ARM from the DSP
- Thanks. This does what I wanted.
On the DSP side: - MW 09:11 AM Software Development: RE: Interrupting the ARM from the DSP
- I think that you are confusing signals and interrupts a bit.
You need to write some kernel module code to register an ISR handler for the CHIPSIG (which may already being used by DSPLINK) and forward/create the signal condition you ar... - MF 08:26 AM Software Development: RE: Interrupting the ARM from the DSP
- Yes, I am familiar with DSPLink and am using it. However, I have time requirement that DSPLink cannot meet. Polling uses too much CPU time. Interrupt would be the most efficient. I just need to know how to connect the CHIPSIG interrup...
- HK 08:01 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- There you are. Note that i had to change the initialization in the code as noted above.
- MW 07:26 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- If you don't mind, could you post your config.gz file?
- HK 05:37 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hey again,
i tried changing it from DMA to PIO. Now, everything seems to work. Device is readable, writable and mountable. Performonce is ok - about 8MB/s either way.
The ethernet problem is gone. I'm not sure where the problem was... - Hey folks,
I'm trying to use a SSD instead of a HDD on the L138F.
I found in the errata that the OMAP-L138 has a problem with SATA devices capable of SATA 3. I'm using a Samsung 840 evo.
The kernel detected the disk once, but ... - AM 02:12 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Jonathan, thank you, I will track your branch.
06/24/2014
- GG 05:41 PM Software Development: RE: Interrupting the ARM from the DSP
- Hello Mary,
I'm not sure what the problem is in your specific example as we almost always use DSPLink to to communicate between the ARM and DSP. We have wrapper classes that allow for passing messages between the DSP and ARM, and uti... - I would like to have the DSP (running BIOS 5) interrupt the ARM (running Linux MDK_2012-08-10)
In the DSP Code: - JC 12:04 PM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Andrey,
Not sure if its any help but I've pushed a work in progress 3.14 branch to our git. Its based off the mainline 3.14.y branch. Haven't been able to get SPI working so the ethernet isn't getting initialized as its configured fr...
06/23/2014
- ES 10:25 AM PCB Development: RE: MityDSP-L138 processor running hot
- All unused connections are no connects.
- ES 09:59 AM PCB Development: RE: MityDSP-L138 processor running hot
- I have attached a plot showing the rise of the supply on the baseboard (channel 2) and the Mity card (channel 1). As you can see there is a droop in the supply on the card. I assume there is a switch mode regulator to generate the 1.8V f...
- MW 09:54 AM PCB Development: RE: MityDSP-L138 processor running hot
- What are you doing with unused connections on the module?
- ES 09:52 AM PCB Development: RE: MityDSP-L138 processor running hot
- It remains hot until the next power cycle. A reset cycle alone does not give an improvement.
- MW 09:15 AM PCB Development: RE: MityDSP-L138 processor running hot
- On non-FPGA variants, DVDD3318_A, DVDD3318_B, and DVDD3318_C are all tied to 3.3V.
Does the issue only occur during reset, or once the unit boots it remains "hot" until another power cycle or reset cycle? - ES 09:07 AM PCB Development: RE: MityDSP-L138 processor running hot
- All our I/O to the card is 3.3V. The OMAP processor has 3 configurable power groups which can be connected to 3.3V or 1.8V. I believe you have them all connected to 3.3V but as I don't have your circuit I cannot verify this. Could you co...
- MW 07:56 AM PCB Development: RE: MityDSP-L138 processor running hot
- Ok.
I suspect the issue may be related to I/O voltage levels (you have I/Os being driven or pulled to a value larger than the bank voltage), or during reset the OMAP-L138 typically pulls most of it's I/O pins (internally) to +VDD of w... - ES 07:51 AM PCB Development: RE: MityDSP-L138 processor running hot
- We are using a baseboard developed for our application. I'm happy to share the schematic. Let me know how to get that to you. The variant we are running is without the FPGA.
I have managed to measure the excess current draw. When it i... - MW 07:06 AM PCB Development: RE: MityDSP-L138 processor running hot
- Hi Ed,
Are you running on a DevKit or on a custom board? Would you be willing to share your schematic (privately to CL, not via this forum page)? Are you using an FDGA variant or processor only variant of the module?
-Mike
- We are some way into the development of using the MityDSP-L138 platform. I recently noticed that about 50% of the time when the module is powered up the OMAP processor runs very hot, >50C. The other 50% of the time it runs relatively coo...
06/21/2014
- AM 03:49 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Jonathan, nothing special only setup kernel config (attached).
I use Yocto Project Daisy toolchain and kernel from git://git.yoctoproject.org/linux-yocto-3.14.git, branch "standard/base".
But I'm not checked all peripherals. Can conf...
06/20/2014
- I am having some trouble with a data acquisition system.
Using MDK_2012-08-10
There are two tasks (among others) that perform the data acquisition. The data is streaming in from the mcBSP and is loaded into a common buffer by the ... - JC 02:12 PM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Andrey, Can you share your linux 3.14 port. What did you have to change to get it working? Are you using device tree?
Thanks Jonathan - Hello,ALL
I want to test the DspFpgaSpi, but not successfully setup,Could anyone give me some instructions?
Before I have successfully tested the GPIO from your help, Thank you very much!
This the VHDL code Setup
//////////////////...
06/19/2014
- GG 09:13 PM FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello,
Your CORE_GPIO_MODULE and base address (0x66000080) do not match one another. The address should be the CORE offset times 0x80 bytes + 0x66000000.
So - LY 02:26 PM FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello.
Ask the same questions about the GPIO
I also try to use the DSP to communicate with FPGA
The follow is the VHDL code for gpio setup
/----------------------------------------------------------------------------/
--Gpio setup... - GG 01:09 PM FPGA Development: RE: Looking for help about SPI core communicate with DSPFPGAspi
- Hello,
- LY 03:27 PM FPGA Development: RE: Help me check out the gpio Setup,It is not work.
- Thank you very much,Mike
- MW 03:11 PM FPGA Development: RE: Help me check out the gpio Setup,It is not work.
- The address for the constructor is not correct. The Address is: the CORE offset times 0x80 bytes + 0x66000000.
In your example, it should be 4*0x80 = 0x66000200.
The code looks OK, though you only need a 0x1 instead of a 0x3 for w... - Hello.
Ask the same questions about the GPIO
I also try to use the DSP to communicate with FPGA
The follow is the VHDL code for gpio setup
/----------------------------------------------------------------------------/
--Gpio setup... - AM 08:54 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- Mike, thank you for fast response.
In Linux 3.14 (from Yocto Project) this leads to disabling cpufreq because it cant locate CVDD regulator.
How you think can I simply change constraints? This doesn't broke my MityDSP?
- MW 08:29 AM Software Development: RE: TPS65023 VDCDC2 and VDCDC3 constraints
- In the hardware, the TPS65023 used for the MityDSP-L138 has the following voltages that are defaulted using the hardware strapping pins:
VDCDC1 -> 1.2 V (core)
VDCDC2 -> 1.8 V (mDDR, DVDD18, DVDD3318_C, FPGA bank voltages)
VDCDC3 -... - Hello,
I use MityDSP-L138F and Linux kernel from git://support.criticallink.com/home/git/linux-davinci.git but want upgrade to 3.14. I found inconsistent config of TPS65023 in board-mityomapl138.c. This file describe tps65023_regulato...
06/18/2014
- JC 12:57 PM Software Development: RE: USB2.0 Host on MityDSP-L138F
- When I enabled the dma I got the following errors when i plugged in the flash drive.
- JC 11:07 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- I was able to scp a 12 MB file without any errors
- JC 11:05 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Also you can buy the cables prebuilt.
USB mini 5 pin to USB A Female
http://www.amazon.com/USB-Female-Mini-Male-Adapter/sim/B0016RNX2I/2 - JC 10:41 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- How were you experiencing the unstable ethernet? Just transferring a file?
- HK 10:36 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- That changed stuff a bit. I now get more messages and the usb-msd driver seems to wake up.
But during initialization, i get error messages of disconnect and reconnect - see the attached log. I'm not sure whether the problem's in the c... - BD 10:12 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hannes, please let us know if this resolves your issue. We actually fixed this same problem on our MitySOM-335x module a few days before you posted your question.
For the sake of those searching the forum in the future, the MitySOM-3... - JC 09:54 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Got it working.
- HK 09:11 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- I don't think so. Udev primarily loads the driver and gets called once the driver does something. In the boot log you can see that the usb enumeration hangs during kernel initialization (usb is compiled in) and before init (and therefor ...
- MW 09:03 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Wondering if this is perhaps a udev issue?
- HK 08:58 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Exactly. But the mass storage driver itself gets loaded and then stalls (no /dev/sd* gets created).
- JC 08:23 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Ok I was able to get things to the point where it will atleast detect the insertion of the flash drive by changing the usb register from MUSB_OTG to MUSB_HOST. I suspect that this is where you are at.
- HK 01:52 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- I tried changing between PIO and DMA before. That changed nothing about the problem - It enumerates the device and then stops.
Another thing:
If I plug in an external USB hub, the Linux detects that. Afterwards if i plug anything in,...
06/17/2014
- Hello,All
I have followed the instruction posted by Michael Williamson. The spi core on FPGA
--https://support.criticallink.com/redmine/boards/12/topics/1672?r=2036#message-2036
I built the FIFO using the IP CORES and put the SPI ... - JC 11:51 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Heres my bootlog. I'm having a hard time getting the mini usb working at all, in either host or peripheral mode. I haven't tried switching from PIO only to the DMA driver you enabled. Did you find that fixed something for you?
- HK 10:11 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- There you are.
That's the dmesg right after startup, with the card reader plugged in during startup. I enabled USB-MSD debug messages, so there's a bit more noise from that.
I'm also getting - TI 09:40 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- OT: Hannes, can you please double check your email address in your profile, I (admin) am getting bounced email warnings for every update to this thread.
thank you
/Tim Iskander - JC 09:27 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Could you post a full boot log? I'd like to compare it with what I'm getting. Also would be nice to see the connection log for the working port for comparison.
- HK 04:16 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hi Bob,
Here's the file.
Thanks
Hannes
06/16/2014
- BD 10:08 AM Software Development: RE: USB2.0 Host on MityDSP-L138F
- Hannes,
Can you upload your kernel .config file? We have seen similar problems on our 335x product line that were traced to an improper kernel configuration.
Thanks,
-Bob
- Hello everyone,
I'm trying to use the USB2-OTG on the MityDSP-L138F as a USB2 Host to connect a few USB-Mass Storage devices.
I'm using the current MDK (2014-01-13) on the supplied Development Board (industrial-i/o). I changed in a...
06/06/2014
- UF 06:36 PM Software Development: RE: DSP HelloWorld
- Flashing the 2014 MDK files solved all the problems. For some reason installing the U-boot bricked my board, but following the wiki on "reprogramming a dead board" fixed it.
I have another question. Is there a sample Makefile for buil... - JC 08:37 AM Software Development: RE: DSP HelloWorld
- The filesystem and kernel that ship preprogrammed on the L138 is quite old. You should have more luck if you flash the u-boot, kernel, and filesystem included in the 2014-01-13 MDK.
Installing U-boot:
https://support.criticallink.co... - BD 10:02 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Silvano, as a test, you can rename the securetty file which should eliminate any restrictions on root logins.
- JC 09:51 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- My securetty file has following at the top of the file which i didn't see in the file you posted.
- JC 09:49 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- I updated to the latest filesystem and got similar results to my previous post.
- JC 08:54 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Testing this on a L138 at my desk. I am able to login as root over ssh using any password including an empty password. But am having no trouble logging in over the serial port.
After setting a password I can no longer login using ... - SB 08:47 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Is there something wrong?
Any idea? - SB 08:19 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Attached you can find:
- a startup screenshot;
- the content of /etc/ folder;
- the file securetty.
Let me know, thanks.
Silvano - SB 08:01 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- From serial I do the access without password but when I write "root" at login it tells me "login incorrect".
From ethernet cable I do the access with "root" and password "mitydsp" but I do not set anything. - TI 08:00 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Normally, this is not a problem. can you check if there is an /etc/securetty file ( http://www.faqs.org/docs/securing/chap5sec41.html )
or log in over the network and then try to log in from the serial console and check the log files in... - MW 07:58 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Did you set a password for the root shell? Normally there is no password by default. How did you set the password?
-Mike
- SB 07:57 AM Software Development: RE: Login uncorrect from serial connection and correct from ethernet connetion
- Does anybady has any suggestion?
It is important for me, not only to have the access from ethernet, but also from serial cable...
06/05/2014
- I'm trying to setup a development environment for the MityDSP-L138 to write DSP code.
I got the DSP HelloWorld test to work, but with a few blocking issues:
1. I had to use the HelloWorld program downloaded from the website. My own... - Dear all,
I have a strange problem.
I hava my MityDSP connected to my pc through both a serial cable and a ethernet cable.
The MityDSP works good. I installed the kernel on the SPI-FLASH and the file system in .jffs2 format on the... - SB 06:24 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- I have corrected all the CRC error rounding the filesize parameters to the correct values.
I have also recompiled the kernel modifyind a little our configuration baseboard-industrialio.c file beacuse we noticed that there was one error ...
06/04/2014
- MW 08:57 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- The filessize should be rounded to 0x800 bytes, which I think should be 0x150C800, not 0x150E000.
-Mike
- SB 08:49 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear all
As I got a lot of CRC errors, here are some question:
1 My .jffs2 file is about 21 MB (22070432 bytes) which corresponds to 0x150C4A0. To copy the filesystem on the target I use the following commands, right?
u-Boot> mw.b 0...
06/03/2014
- SB 08:48 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear Michael,
I tried to run the command you told me. Everything was ok until I copied the fpga_ctrl file on the target machine as you can see in the attached file fpga_ctrl_ontarget.png.
But when I run the "insmod" command I got wha...
06/01/2014
- AS 11:49 AM Software Development: RE: How to run bin application via u-boot?
- > If I knew the answer to using a bin file beyond "go", as you asked before, I would have told you before. :^)
I'm Sorry for my insistence.
> ...
No, the size didn't change much (debug out size is 3.06 MB and release out size is 2.8... - MW 10:19 AM Software Development: RE: How to run bin application via u-boot?
- Hi Ahmed,
If I knew the answer to using a bin file beyond "go", as you asked before, I would have told you before. :^)
So you set the --symdebug:none option and the filesystem grew on your Release build from 2MB to 3MB? That's odd... - AS 04:39 AM Software Development: RE: How to run bin application via u-boot?
- Hi Mike,
I have set the compiler option to "--symdebug:none" and the size of the .out file generated is also 3 MB.
Is there another option to minimize the size of out file? and as i asked you before is there a Uboot command to execute ...
05/30/2014
- MW 11:02 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Did you also rebuild the FPGA drivers? They are not in-tree in the kernel git repository. They are located in the board support package in the MityDSP Developer's Kit.
Let's start with this:
On the build machine: - SB 10:40 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear Michael,
let me know if my way of working is right:
1) I wrote my own baseboard-industrialio.c file as reported in the firts post of this discussion.
2) I recompiled the kernel as reported in https://support.criticallink.com/re... - MW 07:30 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Hello,
We have many customers able to load and run modules with the MityDSP-L138, it's not obvious what the issue is here. I am suspicious that there may have been a problem with the filesystem installation / update (either the modul... - SB 04:00 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear all,
attached you can find a text (LinuxLoading.txt) file where I captured the entire boot together with the screenshot where "Failed" occurs (FailuresLoadingKernel.png).
I also run "uname -a" and the results are in the text fil... - AS 03:45 AM Software Development: RE: How to run bin application via u-boot?
- Michael Williamson wrote:
> Just to confirm, you have the compiler option "--symdebug:none" in your release compile and link options?
> ...
Thanks Mike.
Unfortunately I didn't check this compiler option and now It's my weekend so I'll...
05/29/2014
- AB 04:29 PM Software Development: RE: How to run bin application via u-boot?
- Ahmed,
I believe Mike was suggesting that you build the application as a "release" version without any debugging and see what the resulting application file size is?
I.E. if it was 5MB in debug maybe it's 2MB in release, thus no ne... - MW 04:04 PM Software Development: RE: How to run bin application via u-boot?
- Just to confirm, you have the compiler option "--symdebug:none" in your release compile and link options?
-Mike
- AS 03:51 PM Software Development: RE: How to run bin application via u-boot?
- Hi Mike,
I have tried what you mentioned and it didn't work.
I'll wait your trial.
Thanks in advance. - MW 03:02 PM Software Development: RE: How to run bin application via u-boot?
- I think you need to strip the .out file (make a release version that removes the debugging information).
If I get a second I will try it out.
-Mike
- AB 01:48 PM Software Development: RE: How to run bin application via u-boot?
- Posting some previous direct followup e-mails from the customer.
I have followed the steps of the Starterware wiki ([[https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/StarterWare]]) and I could run elf (UART_MITY_... - MW 10:47 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Hi,
Can you please capture the entire boot up on the console to a text file and set it over?
Or at least run "uname -a" and report the results?
-Mike
- SB 10:38 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Dear Bob,
when I try to load the modules with "insmod fpga_ctrl.ko" I get an error with "Function non implemented" as explanation.
I also found on internet that the insmod error message is caused by either a kernel lacking module sup... - BD 09:30 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Hi Silvano,
Jon was referring to the kernel modules explicitly. The modules need to be installed in your target root filesystem (/lib/$kernelversion) after you copy over the kernel.
The page you reviewed, does mention this, but it'... - SB 08:47 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- I report before that I recompile the kernel every time I made a modificatuon on the baseboard file.
In fact the link you report me is cited by me in my first message.
Maybe there is something wrong in the file or in the compiling.
Cou... - JC 08:24 AM Software Development: RE: Kernel loading module problems MityDSP and FPGA configuration
- Its hard to tell from those error messages whats going on but have you tried recompiling the kernel modules when you made changes to the kernel?
See https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/FPGA_Core_Devic... - Hello everybody.
I am Silvano Bertoldo, I mainly work on the software side of MityDSP and I have a big problem about the linux kernel I am not able to solve. I am very grateful if you can support me or forward the present email to a s... - JC 09:53 AM Software Development: RE: Compiler does not run in VM
- Also our vm does come with the toolchain installed. I'm unsure why you were unable to locate it.
Try looking in /usr/local/oecore-i686
The instructions seem to be missing that you need to run @. /usr/local/oecore-i686/environment-s... - MW 09:29 AM Software Development: RE: Compiler does not run in VM
- Yes. You need to run the 32-bit version in the VM if your VM is a 32-bit architecture.
on your VM type "uname -a". It should tell you the version of the VM architecture.
-Mike - Hello- I'm new to the MityDSP platform and I am having trouble getting the development environment working. I have imported the VM into VirtualBox, and can run the VM. I'm trying to get the environment going for the L138F (ARM9). I fo...
05/28/2014
- Hi everyone,i have MityARM1808F.
I could use "bootelf" command[ex: bootelf 0xc0700000] to run any app.out,but the size of .out format is usually large(in my case is about 5 Mega byte which is too large to be saved on SPI flash with FPGA... - AS 08:54 AM Software Development: RE: UPP ISR is not called
- Finally i could solve this issue by adding the following code :
asm(" mrc p15, #0, r0, c1, c0, #0\n\t"
" orr r0, r0, #0x00002000\n\t"
" mcr p15, #0, r0, c1, c0, #0\n\t");
before calling BIOS_start function.
...