Activity
From 08/14/2026 to 09/12/2026
08/28/2026
- MK 07:07 PM FPGA Development: RE: Programming File Generation
- Hello Mike,
Yes, actually this script A5ED065BB_mesh.pfg - worked.
I've created programming files and was able to boot.
And it is strange that the error message disappeared.
Thanks for your help!!!
Thanks,
Max
08/26/2026
- VD 02:53 PM FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Dan,
I am on mobile right now so cant attach files. BMC is Board Management Controller which handles power sequence of board and also telemetry. In general it drives perstn to root port as well as endpoint.
Altera Confidential
__... - DV 02:43 PM FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Vasu,
The picture still didn't come through. Can you attach it via the "Choose Files" button at the bottom of the post? Also what does BMC stand for when you say "we generally expect PERSTn for RP to come from FPGA IO driven by BMC...
08/25/2026
- VD 05:00 PM FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- [cid:60c940d4-d068-4db2-bd2c-e29f71f55391]
Altera Confidential
________________________________ - MW 11:34 AM FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Vasu,
The link or picture didn't show up. Can you try again or send it to me via email or link?
Thanks,
Mike
- VD 11:33 AM FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Mike,
For Rootport, we generally expect PERSTn for RP to come from FPGA IO driven by BMC on boards as shown below (just an example). So I am looking for logic on board that drives PCIe RP and EP PERSTn.
[cid:a5c32161-6e5b-4a3b-aed9... - MW 09:49 AM FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hello,
Is BK31 a PCIe reset capable pin?
The Carrier board design uses high speed bi-directional analog MUX to allow selecting between HVIO pins or HSIO pins for the LA pins on the FMC interface.
From the Carrier Schematic:
... - VD 05:45 AM FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- To give more clarity on targeted banks:
4C Bank: pin_perst_n
4B Bank: pin_perst_n_1
1B Bank: pin_perst_n_2
- We tried the following combinations for working with a FMC (https://docs.opsero.com/op063/datasheet/overview/)
# To PCIe Endpoints
set_location_assignment PIN_BK31 -to fmc_ep_perst_n_0
set_location_assignment PIN_BW28 -to fmc_ep_pe...
08/21/2026
- MF 05:15 PM FPGA Development: RE: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
- Hi Brady,
Thanks for the details. Both of your fixes look correct and I think you're one step from the real problem (which you pointed out).
You moved the PCIe IP from the left shoreline bank to the right shoreline bank (the FMC), ... - MF 03:23 PM FPGA Development: RE: Programming File Generation
- Max,
Did you try clicking the Generate button? I think the GUI is just bugged stating that the SOF doesn't have the bootloader, however, your pfg file properly declares the bootloader path. Once I clicked generate it merged the SOF wi...
08/20/2026
- Hello Sir/Madam,
I'm trying to create Programming File Generator for our own project based on your example design. Your eaxample design uses Makefile that build, compile and generate programming Files. We have our own scripts to build... - Subject: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
Setup:
Board: MitySOM-A5E, part A5ED-B64-144-SRC-X, mitysom-a5e-ref-base project, pro_2...
08/14/2026
- MF 07:12 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hi Max,
I reviewed your pinout and it looks correct to me.
One thing to mention is that I have posted our FMC example design and Wiki page here: [[A5E-FMC-Example]]. You obviously don't need to use this example design as you presum... - MK 05:33 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hello Mike, thank you so much for your help!!!
I'va attached my pin assignment table with fixes. Can you please take a look and see if exerything is correct. Meanwhile, I'll try to compile with these modifications.
Thanks,
Max - MF 05:20 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hi Max,
You are correct, it is a typo in the FPGA Pin column and not a board issue. Both nets route correctly on the carrier and on the SoM.
Your D12 row is the good one:
* D12 (LA05_N), HVIO route: SoM pin J1-C12, HVIO_6A_12, F... - MK 04:29 PM PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- In addition to previous message, pin H8 also doesn't seems to be right connection (VR31)
- Hello dear Sir/Madam,
I found some small typo in document: MitySOM-A5E-Standard-Development-Kit-Datasheet.pdf (inside document: 60-000098 Rev 1A):
- in table Table 17: J3 Connector Pin Assignments, pin C10 assigned to FPGA Pin: BR22
...