Mity CPU Platforms » MitySBC-Agilex5

10/17/2025

SL 07:30 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Yes, agreed. It would be a good upgrade path without jumping the SOC family. Sung Lim

MW 07:05 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Hi Sung,
With a higher speedgrade option, you can get PCIe x4 gen 4 if bandwidth is a concern and the other end point / root port supports it.
With regards,
Mike Michael Williamson

SL 06:39 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Thank you again for the prompt response. PCIe x4 gen 3 (4GB/s bus limit) should be sufficient for this generation of products. Sung Lim

MF 05:11 PM FPGA Development: RE: MitySOM-A5E PCIe HIP configuration qudstion

Sung,
All of our current Agilex 5 platforms are E-Series, Device Group B devices. Therefore, they only support up to PCIe x4 configurations (not x8). You need a D-series device to support x8.
- Mike Mike Fiorenza

SL 04:58 PM FPGA Development: MitySOM-A5E PCIe HIP configuration qudstion

In the MitySOM-A5E datasheet, "up to six x4 PCIe 4.0 hard IP blocks" are supported.
Can some of the PCIe be configured as x8 (three x8 instead of six x4, for example)? Sung Lim