Activity
From 08/06/2026 to 09/04/2026
Today
- DC 01:32 AM MitySOM-QC6490 Software Development: RE: Device tree additions for custom camera + DSI/touch
- Quick addendum that raises the stakes on this question: we tried sideloading our cross-compiled modules (built against your BSP 1.1 SDK's kernel-devsrc — clean vermagic match) onto a BSP 1.2 device, and they're rejected: the kernel has ...
- Hi,
Starting a new thread based on previous success
We're porting our camera sensor (V4L2 subdev, I2C) and DSI panel + touch drivers — modules build fine against your SDK's kernel-devsrc. Curious what your recommended route is for...
09/03/2026
- DC 06:46 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Hi Greg,
Flashed the prelim build today — mostly excellent news, one blocker on the headline feature:
Working out of the box: headless Vulkan compute (native vulkaninfo : API 1.3.295, driver 0.855.5 — the QLI 1.5 loader-symbol iss... - GG 04:51 AM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Hi David,
Sounds good! Keep me posted if you run into any major issues or inconveniencies (e.g. one thing I forgot to mention is that the prelim build was built with a lot of debug options enabled, so boot times etc are much more ver...
09/02/2026
- DC 10:26 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Greg,
Sorry for the delayed reply. Thanks for this! Looks like it addresses all of our immediate needs. I'll flash the device tomorrow and let you know how it goes. One quick question from my agent :)...
Looks like rawprogram3.xml ...
09/01/2026
- MW 11:45 AM MitySBC-Agilex5 FPGA Development: RE: rbf files from example project gives Error while booting
- Hello,
I am sorry for the inconvenience.
You should be able to use this device instead of a Blaster device if that is a problem:
https://www.digikey.com/en/products/detail/trenz-electronic-gmbh/TEI0004-02/22081849
If it is qu... - TT 11:21 AM MitySBC-Agilex5 FPGA Development: RE: rbf files from example project gives Error while booting
- Thank you for pointing out the issue. The link suggests to program the QSPI NOR via Altera USB-II Blaster.
In the dev-kit I didn't receive any Altera USB-II Blaster. I only received the board, power supply and it's cable, ethernet cab...
08/31/2026
- MW 10:23 AM MitySBC-Agilex5 FPGA Development: RE: rbf files from example project gives Error while booting
- Hello,
The likely issue is that you need to reprogram the SDM and uBoot portion of the bitstream in the SPI NOR FLASH.
There can be an issue where the SDM / and initial bitstream build must match the targeted core.rbf file. If the... - Hi! I’ve received a MitySBC-Agilx5 critical link board. Following are the board details:
*Model* : A5ED-B94-C7F-RC-SBC
*Part Number (written on the agilx-5 SOC)* : A5ED065BB32AI4S
I bought the dev kit so it came with the complete bo...
08/28/2026
- MK 07:07 PM MitySOM-A5 FPGA Development: RE: Programming File Generation
- Hello Mike,
Yes, actually this script A5ED065BB_mesh.pfg - worked.
I've created programming files and was able to boot.
And it is strange that the error message disappeared.
Thanks for your help!!!
Thanks,
Max
08/27/2026
- GG 09:06 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Hi David,
Here is a link to a "prelim build":https://www.dropbox.com/scl/fi/l7u6rl4ygn9oabj2rtzv9/qcom-multimedia-proprietary-image-rb3gen2-core-kit.rootfs.qcomflash-cl-bsp-2.0-wip.zip?rlkey=n8n6xbmnccx51pkzr2jc0ebzg&st=cvq6lz89&dl=0 ...
08/26/2026
- VD 02:53 PM MitySOM-A5 FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Dan,
I am on mobile right now so cant attach files. BMC is Board Management Controller which handles power sequence of board and also telemetry. In general it drives perstn to root port as well as endpoint.
Altera Confidential
__... - DV 02:43 PM MitySOM-A5 FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Vasu,
The picture still didn't come through. Can you attach it via the "Choose Files" button at the bottom of the post? Also what does BMC stand for when you say "we generally expect PERSTn for RP to come from FPGA IO driven by BMC...
08/25/2026
- DC 10:51 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Some ancillary feedback for a QLI 2.0+ image based on working the current dev kit - lmk if you need these broken out separately.
# The stock image ships pulseaudio.service enabled with a config that segfaults on the headless dev kit (... - VD 05:00 PM MitySOM-A5 FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- [cid:60c940d4-d068-4db2-bd2c-e29f71f55391]
Altera Confidential
________________________________ - MW 11:34 AM MitySOM-A5 FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Vasu,
The link or picture didn't show up. Can you try again or send it to me via email or link?
Thanks,
Mike
- VD 11:33 AM MitySOM-A5 FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hi Mike,
For Rootport, we generally expect PERSTn for RP to come from FPGA IO driven by BMC on boards as shown below (just an example). So I am looking for logic on board that drives PCIe RP and EP PERSTn.
[cid:a5c32161-6e5b-4a3b-aed9... - MW 09:49 AM MitySOM-A5 FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- Hello,
Is BK31 a PCIe reset capable pin?
The Carrier board design uses high speed bi-directional analog MUX to allow selecting between HVIO pins or HSIO pins for the LA pins on the FMC interface.
From the Carrier Schematic:
... - VD 05:45 AM MitySOM-A5 FPGA Development: RE: To enable 4 PCIe RP and EP on this board, Need to know the PERSTn signal connections (its very unclear on who drives these signals)
- To give more clarity on targeted banks:
4C Bank: pin_perst_n
4B Bank: pin_perst_n_1
1B Bank: pin_perst_n_2
- We tried the following combinations for working with a FMC (https://docs.opsero.com/op063/datasheet/overview/)
# To PCIe Endpoints
set_location_assignment PIN_BK31 -to fmc_ep_perst_n_0
set_location_assignment PIN_BW28 -to fmc_ep_pe...
08/24/2026
- DC 09:08 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Thank you!
- GG 08:07 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Hi David,
Thank you for the details. I will post a prelim build that meets your requirements here ASAP.
Regarding your question on the dev kit with the newer production-speed RAM, it will ship with what we refer to as "BSP Releas...
08/21/2026
- MF 05:15 PM MitySOM-A5 FPGA Development: RE: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
- Hi Brady,
Thanks for the details. Both of your fixes look correct and I think you're one step from the real problem (which you pointed out).
You moved the PCIe IP from the left shoreline bank to the right shoreline bank (the FMC), ... - MF 03:23 PM MitySOM-A5 FPGA Development: RE: Programming File Generation
- Max,
Did you try clicking the Generate button? I think the GUI is just bugged stating that the SOF doesn't have the bootloader, however, your pfg file properly declares the bootloader path. Once I clicked generate it merged the SOF wi...
08/20/2026
- Hello Sir/Madam,
I'm trying to create Programming File Generator for our own project based on your example design. Your eaxample design uses Makefile that build, compile and generate programming Files. We have our own scripts to build... - Subject: PCIe Root Port bring-up on MitySOM-A5E (A5ED-B64-144-SRC-X) — hard system hang, likely missing GTS reset sequencer for right-side bank
Setup:
Board: MitySOM-A5E, part A5ED-B64-144-SRC-X, mitysom-a5e-ref-base project, pro_2... - DC 06:29 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Hi Greg,
Fantastic — thank you. A preliminary QLI 2.0 build would be very welcome. The interfaces we need functional, in priority order:
*Must-have (our current working paths — regression-sensitive):*
# OpenCL 3.0 on the Adreno 64...
08/19/2026
- GG 11:15 PM MitySOM-QC6490 Software Development: RE: Adreno GPU userspace: newer OpenCL driver (cl_qcom_ml_ops)? + headless Vulkan notes
- Hi David,
Regarding Item 1:
We are currently working on support for for QLI 2.0 as our next release. Below is a table my buddy Opus created based our current release and some internal WIP updates we have:
| | QLI 1.5 | QLI 1.6 ...
08/17/2026
- Hi Critical Link team,
We are evaluating the MitySOM-QCS6490 for a medical imaging product. I've been able to get up and running with the dev kit and I'm experimenting with FP32 ML inference on the Adreno 643 GPU (headless, containeri... - JC 05:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A: Getting the Splash Screen to Appear Earlier
- AM62A splashscreen changes have been merged into https://support.criticallink.com/gitweb/?p=u-boot-ti.git;a=shortlog;h=refs/heads/mitysom-u-boot-2025.01
08/14/2026
- MF 07:12 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hi Max,
I reviewed your pinout and it looks correct to me.
One thing to mention is that I have posted our FMC example design and Wiki page here: [[A5E-FMC-Example]]. You obviously don't need to use this example design as you presum... - MK 05:33 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hello Mike, thank you so much for your help!!!
I'va attached my pin assignment table with fixes. Can you please take a look and see if exerything is correct. Meanwhile, I'll try to compile with these modifications.
Thanks,
Max - MF 05:20 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- Hi Max,
You are correct, it is a typo in the FPGA Pin column and not a board issue. Both nets route correctly on the carrier and on the SoM.
Your D12 row is the good one:
* D12 (LA05_N), HVIO route: SoM pin J1-C12, HVIO_6A_12, F... - MK 04:29 PM MitySOM-A5 PCB Development: RE: MitySOM Standard Carrier Board FMC pin assignment typo
- In addition to previous message, pin H8 also doesn't seems to be right connection (VR31)
- Hello dear Sir/Madam,
I found some small typo in document: MitySOM-A5E-Standard-Development-Kit-Datasheet.pdf (inside document: 60-000098 Rev 1A):
- in table Table 17: J3 Connector Pin Assignments, pin C10 assigned to FPGA Pin: BR22
... - BD 06:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Yocto build support
- Fred,
TI's latest SDK for the MityDSP-L138 processor was released in April 2020. This TI release was based on Yocto Thud.
Any kernel or application vulnerabilities since then would need to be disabled in the kernel or would need t...
08/13/2026
- MF 02:43 PM MitySOM-A5 FPGA Development: RE: PCIE_RP example design - IPs question
- Eleonora,
Thanks for the details. The short answer is that make jic is most likely building from the cores you edited. The Makefile make jic flow is essentially the same as hitting the compile button in Quartus, just with an extra ass... - Good morning,
I'm still trying to run the PCIe_RP example design. As we have discovered, the device that is on the board is not the one that the project was generated for, so when I changed the device Quartus needed me to update the cor...
08/07/2026
- FW 03:00 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Yocto build support
- I also looked into TI Yocto support for the L138 (meta-ti, Arago?). AI indicated they stopped support about 2017 (Morty?). As you have more inroads with TI than me or AI, can you confirm this? What is the latest Yocto/Kernel supported by...
08/06/2026
- MK 06:31 PM MitySOM-A5 FPGA Development: RE: HPS to FPGA Manager (Memory-Mapped) question
- Hello Mike,
Thanks a lot for your reply.
We used this offset 0x4000_0000 (1 GB) and we got the expected reply from/to our registers!!!
Thanks for your refferal to memtool. We tested memtool, but need our application as well.
Than... - MF 06:08 PM MitySOM-A5 FPGA Development: RE: HPS to FPGA Manager (Memory-Mapped) question
- Hi Maxim,
Thanks for sending the project along, that made this much easier to answer.
*On fpgaregister.h.* Yes, it works for the full HPS to FPGA bridge. There is nothing in that header that is specific to the Lightweight bridge, i... - Hello dear Sir/Madam!!!!
we have again some question.
Based on your A5ED-B64-144-SRC-X/mitysom-a5e-ref-dma Example Desigmn, we added custom DMA Loopback (this is already working for us) and additional HPS to FPGA Manager 64 bit Data,...