Activity
From 02/21/2026 to 03/22/2026
03/21/2026
- Hello,
My carrier board uses several QUP pins for I2C, UART, and SPI. How do I configure them? I prefer a device-tree solution over a userspace solution.
03/20/2026
- Hello,
I am extending the BSP with my own layer. It seems like whenever I make a change, a lot of unrelated files get recompiled (for example cameradlkm-1.0.qcom-r0, qcom-displaydlkm-git-r0, qcom-pal-git-r0, qcacld-wlan-git-r0, ...). ...
03/19/2026
- TT 09:53 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can't read state of output GPIO pins
- Thank you, that would explain it. We ended up setting the pin regardless of the current state. It was an easier change for us.
Tim
03/16/2026
- JC 06:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Can't read state of output GPIO pins
- At least for the AM62x, Pins that need to be read, must be pinmuxed as PIN_INPUT*. The only difference between the PIN_OUTPUT and PIN_INPUT #define is whether the input buffer is enabled.
- Hi,
On an AM62x we have a gpio pin (/dev/gpiochip2, line 10) muxed as an output pin. Our application checks the state of this pin to see if it is in the desired state before setting it if needed. Unfortunately the pin state is always ...
03/12/2026
- MF 09:46 PM MitySBC-Agilex5 FPGA Development: RE: building FPGA and bootloader
- Eleonora,
Our Makefile is currently configured to support Linux. So installing Quartus inside of WSL or a Linux VM would make following our Wiki instructions easier.
That said, you could try the following to convert your JIC the... - Hi,
I have Quartus Pro 25.3 with the fix, but it's installed in Windows. If I compile the ref-base project in Windows, I get sof file and when I try to convert it to jic - I get an error that the bootloader configuration is missing and ...
03/03/2026
- MW 08:51 PM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Hi Eleonora,
Are you trying to run EP or RP?
The GBTCLK0_M2C_P/N on FMC D4/D5 is run to REFCLK_GSTR4B_CH1p/n (AV16 AV21) of the FPGA.
The GBTCLK1_M2C_P/N on FMC B20/B21 is run to REFCLK_GSTR4A_CH1p/n (BB16 BB21) of the FPGA.
... - EH 08:26 PM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Thank you, Mike.
I was asking about the schematic, because I don't have information about all the pins that are connected on the PFGA. We are working with Arrow, so I'll ask them for schematic, but can you answer few more questions abo...
03/02/2026
- MW 08:14 PM MitySBC-Agilex5 FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Hello Eleonora,
To confirm, are you using the MitySBC hardware? If so then the three possible banks for PCIe x4 would be:
Bank GTSL1B (M.2 Connector)
Bank GTSR4B (FMC DP0->DP3)
Bank GTSR4A (FMC DP5->DP7 .... reversed connectio... - Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the...
02/27/2026
- DV 08:18 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Are you using the "Makefile":https://support.criticallink.com/gitweb/?p=mitysom-5csx-ref.git;a=blob;f=dev_5csx_h6_42a/Makefile;h=7d61fe6112ad18bf792a770dd3a5721078b5c475;hb=refs/heads/23.1-stable at the top of the FPGA proje... - XS 07:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Thanks for your support, I build a envirment with Ubuntu 22.04 and Quartus 23.1; and finish re-build uboot. But when i try to generate SD image file, I got below:
$ make sd_image
scripts/kconfig/conf --synccon...
02/26/2026
- TC 02:58 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- Got it thank you!
Tom - MF 02:52 PM MitySBC-Agilex5 Software Development: RE: Eclipse Application
- This question was posted and answered on thread: https://support.criticallink.com/redmine/boards/72/topics/7175
If you have any further questions regarding this topic don't hesitate to reach out.
02/25/2026
- JC 05:05 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Great glad it worked. Hopefully the dtc command examples will be helpful for you and others as well
- BH 04:59 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- I md5sum'ed the SD dtb and the emmc dtb, they were in-fact different. I re-copied the files and now it is working. I guess in some step I mixed up which device I had updated the rootfs on. I think this is solved. Thank you for your help!
- JC 04:24 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- It would also be a good idea to md5sum the emmc and sdcard versions of the tfc dtb to make sure they are infact identical.
- JC 04:23 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Thanks Ben, I hadn't realized that.
Lets make sure the tfc device tree file contains what you expect it to.
Do you have the "dtc" tool on the filesystem, I think we include it by default?
You can use it to inspect the compiled d... - MW 03:35 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- can you also post the dtb file?
- BH 03:21 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Sorry, I just posted the u-boot log, it does indeed boot. Per the u-boot log it claims to load my dtb but the differences in the device tree once in linux are not present, here's just one example, if in SD boot I see my device tree refle...
- JC 02:43 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- > Some progress made, it now finds the file but still does not load it.
It looks like it did load it from the eMMC so that is indeed progress
02/24/2026
- BH 11:06 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Jonathan,
Some progress made, it now finds the file but still does not load it.
Here are the dtbs (the "-tfc" is mine) - JC 10:47 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Yeah please share the console log during the boot attempt.
To get a bit more debug info, enable xtrace in u-boot before running boot - BH 10:38 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Jonathan,
Thanks for your reply. Unfortunately, that did not solve the problem. The system fails to find the file and then proceeds to boot with the bootloader image fdt.
I have confirmed the dtb I want is located in the user par... - JC 09:26 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: AM62A eMMC Boot - Kernel Device Tree
- Hi Ben,
The device tree file that gets loaded is set in the fdtfile variable. You should be able to update it to match your device tree. - I’m working with the AM62A SoM and a Yocto development environment, switching between the CL devkit and custom hardware.
I am trying to boot the system with a modified device tree. This works fine from SD-cards but when I follow the ... - WE 09:39 PM MitySOM-QC6490 PCB Development: RE: Auto start
- When talking about input power to the SOM that would be the 3V7-BAT rail.
There would be a delay between power being applied (on 3V7-BAT) and when the SOM would be monitoring the POW-BTNn but we haven't quantified this yet. We will se... - NO 09:14 PM MitySOM-QC6490 PCB Development: RE: Auto start
- Thanks!
Does power have to be high for a certain amount of time before the power-on pulse? If so, which rail and for how long?
Or can POW_BTNn be held low at startup, and released after 400ms? - WE 07:30 PM MitySOM-QC6490 PCB Development: RE: Auto start
- The only "automatic" power on we have implemented so far is software control from an Arduino.
There are two main stipulations on the POW-BTNn:
# The power on pulse must be greater than 400ms.
# A power button press of 10s is a syste... - I'm using DC power and I'd like to auto-start the SOM when power is applied. What are the requirements for the signal on POW_BTNn?
Is there an example auto-start circuit I can copy?
02/23/2026
- DV 08:07 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Boot *Makefile* (around line 40), *or* it could be related to your build environment: it looks like you're using our Ubunt... - XS 07:03 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout
- Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang - JC 04:01 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Glad it worked. Thanks for closing the loop
- PS 10:44 AM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Problems writing to MCU_GPIO0_19 and MCU_GPIO0_20
- Just a quick note to say thanks to everyone for solving this issue this quickly
We have fitted the pullups to our board and can now see the outputs toggling
Paul