Activity
From 11/09/2025 to 12/08/2025
12/08/2025
- JC 09:39 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Uart issue in Am62P
- Hi Rajkumar,
Just following up - ZM 05:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet PHY configuration and SSH access
- Hi Atef,
The image you downloaded should have an SSH server (OpenSSH) running by default, yes. @ps@ by default doesn't show all processes, which is why the grep in your screenshot didn't find it. Running @ps -A@ or @ps aux@ should con... - Hello,
I am working with a MitySOM-5CSx module on my own custom carrier board and I am seeing different behavior depending on which SD card image I use. I would appreciate your help to understand the correct configuration.
+*Hardware...
12/05/2025
- JC 09:55 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot I2C Speed Command [MityDSP L138]
- 2019 with i2c mods
Flashing u-boot based on https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Updating_devkit_to_latest_MDK - JC 09:45 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot I2C Speed Command [MityDSP L138]
- By default the 2019 u-boot doesn't support multiple i2c buses. Though I was able to tweak some code to seemingly get it working, however I don't have devices on i2c1 to determine if its actually working.
- JC 09:29 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot I2C Speed Command [MityDSP L138]
- Testing the 2019 u-boot and i2c speed command does appear to be supported though I didn't scope the lines to prove it was changing speeds.
- JC 07:47 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Configuring OMAP-L138 peripherals from uBoot
- The latest L138 RTOS SDK 06_03_00_106 for the L138 does have documentation for MCASP and a bunch of other peripherals.
https://www.ti.com/tool/PROCESSOR-SDK-OMAPL138#downloads
https://software-dl.ti.com/processor-sdk-rtos/esd/docs/06... - JC 04:17 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Configuring OMAP-L138 peripherals from uBoot
- Hi Michael, I created a e2e question asking TI about MCASP support on the DSP. https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1595231/omap-l138-d...
12/04/2025
- MB 08:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Configuring OMAP-L138 peripherals from uBoot
- Jonathan,
If StarterWare/BareMetal are against the grain, please point me towards DSPBios code/examples that use McASP. Which version of DSP/BIOS are you using? When making a new project in CCS, do you tell CCS to target an OMAP-L138 or... - JC 07:27 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Configuring OMAP-L138 peripherals from uBoot
- Hi Michael, We have only used the DSP with TI's DSPBios RTOS. It should already have abstraction layers for most of those peripherals.
12/03/2025
- JC 10:46 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot I2C Speed Command [MityDSP L138]
- Michael B wrote:
> Hi All,
> ...
In the 2009 u-boot, i2c set speed is not implemented. There are provisions for architecture specific implementations but there are none relevant for the L138.
https://support.criticallink.com/gitweb... - MB 09:39 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uBoot I2C Speed Command [MityDSP L138]
- As a follow up, is there any way to test I2C 1 bus through uBoot?
- Hi All,
I'm in the middle of debugging some I2C issues and was curious how the uBoot i2c speed command is handled. It seems to take/return Hz, does that relate to baud rate, bitrate, or just SCL frequency?
The i2c speed is defaulting... - Hi all,
I am interested in running a bare metal application on just the DSP core, and would like some help configuring as many of the peripherals (I2C, McASP, UART, DMA, etc.) from within uBoot instead of in the DSP code initialization....
12/02/2025
- AF 12:47 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Issue booting encrypted bitstream on MitySOM-5CSx evaluation board
- Thanks, it works.
12/01/2025
- MF 04:20 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Issue booting encrypted bitstream on MitySOM-5CSx evaluation board
- Atef,
Can you make sure you have the MSEL set appropriately per the table below?
!image.png! - Hello,
I am trying to test bitstream encryption on a MitySOM-5CSx evaluation board and I am running into an issue during boot.
Here is what I have done so far:
In Quartus, I enabled bitstream encryption and generated an encrypted RBF ... - MW 12:30 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: Uart issue in Am62P
- Hi Rajkumar,
Is the only difference between the AM62P working and not the use of the application code vs. the loopback code?
Are you testing with the same data / BAUD rate in loopback vs. application? Same hardware configuration?
... - Hi,
We are working with the Critical Link AM62P and AM62a SoM and have installed Debian 13 on am62P the system. We are currently using UART5 for communication, and we are facing an issue specific to the AM62P module.
Initially, we ...
11/28/2025
- AF 03:57 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Using the design security for MitySOM-5CSX
- Hello,
I would like to encrypt the FPGA bitstream on the MitySOM-5CSX. I have been referring to Intel’s application note AN557 (Using the Design Security Features in Intel FPGAs) to understand how to enable bitstream (.rbf file) encrypt...
11/19/2025
- JI 12:43 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX
- Seth,
I got the GPIO pin on the FPGA side to work as you described. This is just as good as having an LED because the whole point was to have an example to study how the GPIO is triggered from the linux side,i.e. how the command "worms...
11/14/2025
- MF 08:59 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Atef,
Okay that makes sense! In that case, I would look into Arm Developer Studio then. You should be able to obtain an evaluation license and it should be able to accomplish what you are asking for. There are potential open-source so... - AF 08:50 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Mike,
Thank you for your response, I’ll have a look at it.
I was focusing on using JTAG because I’m having an issue with SD-card boot on the carrier board I designed.
Thanks again for your help. - MF 04:03 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Atef,
If you see our Wiki page here: https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki we post full SD card images for the development kits. These SD cards will use U-Boot as the bootloader which the HPS loads first t... - AF 03:50 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Mike, Thanks for your response. Yes, I was trying to load the compiled C code binary directly to the HPS via JTAG. Since there is no tutorial available for that method, could you please send me (or point me to) your tutorial explaining h...
- MF 03:42 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Atef,
Glad to hear you resolved your JTAG issue. Can you elaborate on how you are trying to load the HPS portion? Are you trying to load binaries directly to the HPS via JTAG? Unfortunately we do not have any tutorials at the moment t... - AF 10:31 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Thank you Mike, the system works by reversing the USB Blaster connection. I have another question please: Do you have a tutorial that explains how to load the HPS portion using WSL on Windows? Thanks.
11/12/2025
- MF 04:23 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Clarification regarding LED 4 on MitySOM-5CSX DevKit
- Atef,
From your picture, it looks like you have the JTAG pod plugged in backwards. Pin 1 on your ribbon cable does not align with Pin 1 on the JTAG adapter board.
Please try rotating your pod connection and report back.
- Mike - AF 04:13 PM MitySOM-5CSX Altera Cyclone V FPGA Development: JTAG programming issue on MitySOM-5CSX DevKit with Quartus (Windows 11)
- Hello,
I’m trying to program a MitySOM-5CSX board via JTAG using Quartus on Windows 11, but I encounter an error immediately when starting the operation.
I'm using :
-Tool: Quartus [version], Windows 11
-Interface: USB-Blaster [I...