Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

02/27/2026

DV 08:18 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
Are you using the "Makefile":https://support.criticallink.com/gitweb/?p=mitysom-5csx-ref.git;a=blob;f=dev_5csx_h6_42a/Makefile;h=7d61fe6112ad18bf792a770dd3a5721078b5c475;hb=refs/heads/23.1-stable at the top of the FPGA proje... Daniel Vincelette

XS 07:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
Thanks for your support, I build a envirment with Ubuntu 22.04 and Quartus 23.1; and finish re-build uboot. But when i try to generate SD image file, I got below:
$ make sd_image
scripts/kconfig/conf --synccon... Xiang Shuai

02/23/2026

DV 08:07 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
Sorry about the delay. It looks like this is either due to a missing or unexpected character in the U-Boot *Makefile* (around line 40), *or* it could be related to your build environment: it looks like you're using our Ubunt... Daniel Vincelette

XS 07:03 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
Do you have any update, what I can do now?
BR,
Xiang Xiang Shuai

02/09/2026

XS 03:49 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,

clipboard-202602091046-ikfkk.png
please see attached picture, that's a typo when I fill this page.
BR,
Xiang Xiang Shuai

02/06/2026

DV 10:17 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following: Daniel Vincelette

XS 09:11 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defconfig
Makefile:40: *** missing separator. Stop
what can I do?
BR,
Xiang Xiang Shuai

02/05/2026

DV 09:42 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually change it. Here are our build instructions for the preloader and u-boot: https://support.criticallink.com/redmine/projects/mi... Daniel Vincelette

XS 09:04 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout

Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot. Could you give me a detail instruction ? Thanks!
BR,
Xiang Xiang Shuai