Activity
From 06/03/2024 to 07/02/2024
07/01/2024
- MB 09:16 PM Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)
- Hi Jonathan,
Thank you for the response, please let me know what you find out! The system as a whole must be under 1W average while operating, and very low <50mW when in sleep. When operating, it will be performing some audio signal pr... - JC 07:05 PM Software Development: RE: MityDSP-L138 Power Draw in Deep Sleep? Waking ARM core from DSP core? Power and Sleep Controller (PSC)
- Michael Bisbano wrote:
> Hi all,
> ...
Hi Michael, I did a bunch of work for the MitySOM-335x for sleep mode but am not sure about the L138. I'll ask around and let you know what I find out.
>
> ...
In the meantime could you clarif... - Hi all,
I was wondering if anyone had data on power draw for the MityDSP-L138 in deep sleep? My application is battery powered and we are determining if it is more feasible to have an external circuit on our custom baseboard control p... - JC 03:49 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Fred Weiser wrote in message#6688:
> Changing the timer is probably not in my best interest; my project supports down to 1200 baud with packets up to 256 in length (that's over 2 seconds). I see two possibilities:
Can you try it just t...
06/27/2024
- FW 09:06 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Changing the timer is probably not in my best interest; my project supports down to 1200 baud with packets up to 256 in length (that's over 2 seconds). I see two possibilities:
# Add RTS/CTS back into the pinmux, disable the 485 confi... - FW 06:12 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Here's the snip:
- JC 05:45 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Looks like wait_for_xmitr has a 10ms timeout, this might explain why the TXEN is enabled for a constant time. At low baud rates the 10ms timeout would be more of an issue I suspect.
Note in newer kernels, the stop_tx call checks the ... - JC 04:19 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- What does your pinmux look like for UART2?
- FW 03:36 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Please see two attached scope traces; the second with a 7 character buffer, the first with a 16 character buffer. I wanted to provide some objective evidence to your comments above... Notice the RTS active time is the same; it is that wa...
- TI 02:31 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- It looks like (in the 3.2 kernel anyway) the only serial port driver that supports the delay_rts_after_send option is the atmel_serial.c, and it uses features of the UART to implement it.
You could implement this in the 8250 driver and ... - FW 01:46 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Thanks for the ideas; I'm looking into the code cited above now; I don't have any new news there at this time.
However, here is some additional info: when the RTS line drops early, it may be a partial character, or sometimes as many ... - TI 01:05 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- My suspicion is that the register read in wait_for_xmitr() is "lying" and the UART is actually still serializing the data even though it says the TSR is empty.
My suggestion is to put a delay of 1 char before releasing the GPIO. This co... - JC 08:47 PM Software Development: RE: RS485 Direction Control on UART1
- Seems like it could work. Good find.
- MB 07:17 PM Software Development: RE: RS485 Direction Control on UART1
- I did come across this application note from TI: https://www.ti.com/lit/ug/tidubw6/tidubw6.pdf?ts=1719509747706
(if the link is broken in the future to others with this need, the article is titled: "TIDUBW6 - June 2016: TI Designs Autom...
06/25/2024
- JC 09:59 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- The kernel driver code for RS485 support can be found here: https://support.criticallink.com/gitweb/?p=linux-davinci.git;a=blobdiff;f=drivers/tty/serial/8250.c;h=fd19e7d82137f1bcccae36b6cade7878267fc8f9;hp=eeadf1b8e093202234b30c688490da2...
- FW 06:58 PM Software Development: RE: Serial port 2 issue, RS485, RTS drops to early
- Seems a "paste" didn't work as expected...
SER_RS485_USE_GPIO is the same as 1<<5 - We are having a problem with serial port ttyS2 on our L138 SoM which I believe resides in the Linux driver or the TI serial port support. The port is used as a RS-485 interface running Modbus, which requires using the RTS line to control...
06/20/2024
- JC 07:57 PM Software Development: RE: RS485 Direction Control on UART1
- How long are you looking for?
The kernel documentation mentions getting extended distance for rs232 by using UTP cat 5 cable. Or using a shield low-capacitance wire. Also mentions using line drivers to get larger distances.
https://... - MB 03:43 PM Software Development: RE: RS485 Direction Control on UART1
- Hi Jonathan,
thanks for the quick response. I will look into the 8250 driver, it might be useful (if only for my runtime code). I expected a hesitant response with regard to this scheme, but half duplex RS485 is unfortunately the mos...
06/19/2024
- JC 07:09 PM Software Development: RE: RS485 Direction Control on UART1
- The serial 8250 driver has an rs485 mode which we extended to allow using a gpio to generate a RS485 TX enable. However this was intended to be setup at runtime for a separate interface and not for the debug console. Though you may be ...
- Hi all,
My application requires installation embedded in a battery power system with long wire. I would like access to UART1 over the wire, which we have decided to use half duplex RS-485 for. Is there a way to make the UART1 integrat...
06/10/2024
- MW 11:08 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read request is generated by the DSP to the EMIFA space, a command/request is generated to the cross-bar controller. The controll... - KB 07:52 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk speed of FIFO.
MDK_2014-01-13/sw/ARM/u-boot-mitydspl138/board/davinci/mityomapl138/mityomapl138.c
In the file abo...
06/05/2024
- GG 09:05 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code requires transitions on i_ema_cs5_n or i_ema_oe_n in order to read out new FIFO samples. These transitions are most likel... - KB 12:42 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown below.
06/03/2024
- JC 03:08 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem
- The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If the DMA engine is modifying RAM outside of the DSPs knowledge, then the DSP needs to be informed that its cache of that m...
- hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading the DSP application through ARM. (Thank you to those who helped.)
The work I am currently doing is accumulating data ...