Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)

06/19/2024

JC 07:09 PM Software Development: RE: RS485 Direction Control on UART1

The serial 8250 driver has an rs485 mode which we extended to allow using a gpio to generate a RS485 TX enable. However this was intended to be setup at runtime for a separate interface and not for the debug console. Though you may be ... Jonathan Cormier

MB 04:36 PM Software Development: RS485 Direction Control on UART1

Hi all,
My application requires installation embedded in a battery power system with long wire. I would like access to UART1 over the wire, which we have decided to use half duplex RS-485 for. Is there a way to make the UART1 integrat... Michael B

06/10/2024

MW 11:08 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

There is a cross-bar that sits between EMIFA on the L138 and the DSP / ARM / peripheral masters.
When a read request is generated by the DSP to the EMIFA space, a command/request is generated to the cross-bar controller. The controll... Michael Williamson

KB 07:52 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
We will conduct the above experiment later.
Currently, we are trying to increase the RD Clk speed of FIFO.
MDK_2014-01-13/sw/ARM/u-boot-mitydspl138/board/davinci/mityomapl138/mityomapl138.c
In the file abo... Kyungguk Bok

06/05/2024

GG 09:05 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Hello,
Based on the FPGA code you shared I believe that the primary issue you are having is that your FPGA code requires transitions on i_ema_cs5_n or i_ema_oe_n in order to read out new FIFO samples. These transitions are most likel... Gregory Gluszek

KB 12:42 AM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

Thank you for answer.
As you suggested, read Cache_and_Memory and
We proceeded by modifying the source as shown below. Kyungguk Bok

06/03/2024

JC 03:08 PM Software Development: RE: FPGA (FIFO) -> DSP (DMA) transfer problem

The fpga guys can step in if I've missed something but it looks to me like your missing cache invalidate calls. If the DMA engine is modifying RAM outside of the DSPs knowledge, then the DSP needs to be informed that its cache of that m... Jonathan Cormier

KB 08:57 AM Software Development: FPGA (FIFO) -> DSP (DMA) transfer problem

hello.
I am posting because I have a question related to DMA.
The last CCS issue was not resolved, so I am loading the DSP application through ARM. (Thank you to those who helped.)
The work I am currently doing is accumulating data ... Kyungguk Bok