Activity

From 03/09/2014 to 04/07/2014

JP 12:00 PM Software Development: RE: Net: No ETH PHY detected!!!: I used the serial flashing program to erase the memory before flashing u-boot again and this time phy eth is detected and networking works normally.
I'm sorry for the trouble. Jordi Perez Serra
JP 10:53 AM Software Development: Net: No ETH PHY detected!!!: Hello,
I have a mitydspl138 board. I accidentally overwrote some of the u-boot memory. I used the serial programmer to re-flash u-boot
https://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Reprogramming_a_Dead_Board
... Jordi Perez Serra
MW 07:43 AM FPGA Development: RE: UPP Sample Code needed: For the FPGA interface, you could take a look at the "Vision Framework Design FIles":https://support.criticallink.com/redmine/projects/indio/wiki/Vision_Framework_Kit. This uses the UPP to push video data from the FPGA to the OMAP-L138. ... Michael Williamson
MW 07:39 AM Software Development: RE: DSP- EDMA Transmission problem: Hello Mr. Krawczyk,
You can interface with the UPP directly as you have described and by looking through the TRM, or you can try to use the tcDspUpp.cpp class, which was intended to help a little with that but it certainly not require... Michael Williamson

RK 09:35 AM Software Development: RE: DSP- EDMA Transmission problem: Hello Mike,
The UPP seems to be an optimal solution. However, It looks like configuring the UPP is a bit complex. I can see there is a tcDspUpp.cpp file in a core library and some usage of its methods in tcDspFpgaCameraLink.cpp.
My qu... Rafał Krawczyk
AS 01:26 AM FPGA Development: UPP Sample Code needed: Hi everyone,
I need a sample FPGA code for UPP(Supported by Critical Link) with it's UCF file(including timing constraints).
Thanks in advance. Ahmed Shaaban

MW 05:23 PM Software Development: RE: DSP- EDMA Transmission problem: Actually,
I was going to suggest transferring to IRAM, or if you need to transfer to DDR, doing a chained transfer:
EMIFA -> IRAM, then IRAM->DDR
Sounds like you've seen improvement in moving into the IRAM. Unfortunately, our Q... Michael Williamson
RK 04:53 PM Software Development: RE: DSP- EDMA Transmission problem: To be more precise,
Is there any way to change the EDMA3 configuration to reduce transfer time ? I want to transfer the data from FPGA's 16-bit EMIFA bus to IRAM, where I think the memory bus is 32-bit. For now I am using the unchanged ... Rafał Krawczyk

RK 05:20 AM Software Development: RE: DSP- EDMA Transmission problem: Hello again,
I am writing because I have the following problem:
I succesfully transfer the data, but the transfer time seems to take too much time. I am transferring 4096 16-bit words using the modified FPGA EMIFA interface that takes ... Rafał Krawczyk

RK 03:16 PM Software Development: RE: DSP- EDMA Transmission problem: Solved !
You can use the IRAM section. It is disabled as cache in the current configuration .tcf file.
Best regards Rafał Krawczyk

MW 09:57 AM Software Development: RE: GEL-file for MityDSP-L138F: Yes. By default, the core should be 1.2V on power up.
-Mike
Michael Williamson
OM 09:38 AM Software Development: GEL-file for MityDSP-L138F: Hi,
that gel-file need to use for mitydsp-L138F with 1.2 V Core?
Thanks Oleh Mela

FT 08:05 PM FPGA Development: RE: Manage LX16 and LX45 at runtime: Thanks a lot Mike!
As usual, your support is impressive!
Ticket close.
-François François Tremblay
MW 05:18 PM FPGA Development: RE: Manage LX16 and LX45 at runtime: The model number for the part should be readable in the factory configuration information in the I2C prom. The model number includes a letter code for the FPGA type for the SOM. There is a factoryconfig utility program that can be run ... Michael Williamson
FT 04:55 PM FPGA Development: Manage LX16 and LX45 at runtime: We have a product based on MityDSP-L138F using either LX16 and LX45 fpga cores.
Q1) Can we detect which FPGA core is running at runtime from Linux?
Q2) Is program_fpga.sh script and fpga_ctrl.ko module are able to handle both at ru... François Tremblay

AS 07:08 PM Software Development: Error while connecting to ARM9: Hello everyone,
I have a MityARM 1808F and I am facing a strange issue which is as follows:
* when I am trying to connect to ARM +without+ stopping the uboot (from booting linux), I receive this error Ahmed Shaaban

RK 05:13 PM Software Development: RE: DSP- EDMA Transmission problem: Hello Mike,
Thank you very much for your response.
I have a question before I transfer to other place than L2 Cache. I found in the forum the information about the usage of memory:
https://support.criticallink.com/redmine/projects/... Rafał Krawczyk

MW 07:25 AM Software Development: RE: DSP- EDMA Transmission problem: Do you see this affect if you transfer to a different place in DDR (instead of the L2 SRAM)?
Are you still enabling the DSP L2 Cache? You can't enable L2 Cache and also try to use it directly as shared RAM unless you reduce the cac... Michael Williamson
RK 07:19 AM Software Development: RE: DSP- EDMA Transmission problem: Hello Michael,
It looks like edma is causing that. When I turned the edma off and used the data without transferring it to L2_Cache. That is, I am attempting to transfer the data block from 0x66000880 to L2_Cache in 0x11820000 for perfo... Rafał Krawczyk

MW 03:44 PM Software Development: RE: DSP- EDMA Transmission problem: It sort of sounds like there is a memory leak somewhere. Are you thinking it's in the DspQDMA routines?
-Mike Michael Williamson
RK 03:29 PM Software Development: RE: DSP- EDMA Transmission problem: Hello again,
There is another symptom in my application that occurs. I am viewing the size of heap in the MEM in the RTOS object view (ROV).The size of free memory in heap is drastically low just after the EDMA transfer is finished (and... Rafał Krawczyk

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Mity CPU Platforms » MityDSP-L138 (ARM9 Based Platforms)