Activity
From 07/21/2011 to 08/19/2011
08/19/2011
- MW 01:40 PM Software Development: RE: Transfer files to card from PC via usb ? instead of ethernet ?
- You will need to rebuild the kernel (and install it on your system) such that it supports USB mass storage devices and ensure that the FAT filesystem is enabled.
You can download a new kernel image (painful, I understand) to run out o... - TN 01:33 PM Software Development: RE: Transfer files to card from PC via usb ? instead of ethernet ?
- Thank you very much for the information. After using USB 1.1 port as host port, connecting a USB flash drive, I have problem as described here : http://support.criticallink.com/redmine/boards/10/topics/666
lsmod shows empty list and the... - MW 07:29 AM Software Development: RE: Transfer files to card from PC via usb ? instead of ethernet ?
- USB support for the OMAP-L138 is fully described in the User Guides provided by the TI on it's "OMAP-L138 Processor":http://focus.ti.com/docs/prod/folders/print/omap-l138.html web page.
USB1 (pins 23,25) is a HOST only USB 1.1 complia...
08/18/2011
- TN 03:33 PM Software Development: RE: Transfer files to card from PC via usb ? instead of ethernet ?
- Hi,
USB stick is not connected. It is a USB cable only.
The configuration is like this :
UART to USB via FT232R : This works..able to login as root.
USB1 pins 23,25 pinhead to USB : This connection does not get recognized when c... - MW 02:46 PM Software Development: RE: Transfer files to card from PC via usb ? instead of ethernet ?
- Can you provide a reference schematic to your baseboard?
Do you have a USB memory stick connected to one of the two ports?
-Mike
- Hi,
I have two USB cables connected to baseboard.
Using one, I am able to connect to console and login root@mitydspl138
dmesg output is here :
usbcore: registered new interface driver usbfs
usbcore: registered new interface driv...
08/17/2011
- TN 06:33 PM Software Development: RE: MityDSP GUI
- Thanks for the reply. Sorry for the confusion.
We have our own baseboard with mitydsp connected to it. Using UART to USB it is now detected on the PC. Thanks for the help. - MW 12:53 PM Software Development: RE: MityDSP GUI
- Hi Thomas,
I'm a little confused. The MItyDSP-L138 card is a "system on module (SOM) or computer on module (COM) ":http://en.wikipedia.org/wiki/Computer-on-module, not a "single board computer (SBC) ":http://en.wikipedia.org/wiki/Sin... - TN 12:41 PM Software Development: RE: MityDSP GUI
- Hi Mike, Thanks for the reply. We do not have the baseboard. Only the mitydsp-l138 card. Can we still communicate with it directly ? For example, USB to ethernet ? Is that possible ?
Thanks.
TN - MW 07:33 AM Software Development: RE: MityDSP GUI
- The Industrial I/O card (the MityDSP-L138 development kit baseboard) should have come with a 10 pin ribbon to DB-9 connector. That plugs into the connector next to the power input terminals. The interface requires a NULL modem serial c...
08/15/2011
- TN 05:08 PM Software Development: RE: MityDSP GUI
- Yes, we have OMAPL138 product. Is there a user interface that works with this card ?
We are trying to use UART interface to communicate.
- TC 05:02 PM Software Development: RE: MityDSP GUI
- Hi Thomas -
The MityDSP GUI is used only with our 6711 and 6455 based product. I believe you have an OMAPL138 or AM1808 based product, is this correct?
Thank you -
Tom - Hi,
Is the MityDSP GUI , part of hardware shipment ? or do we have to buy it separately ? Can I download it from criticallink ?
Thanks
TN. - TI 02:43 PM Software Development: RE: Eclipse CDT Builder problem when set up for cross compile
- Fred,
There's a good chance that your bashrc file is no being read when you start it from the launcher. I don't remember the exact rules, but you may need to put the setup in your .bash_profile instead. - FW 02:35 PM Software Development: RE: Eclipse CDT Builder problem when set up for cross compile
- The angstrom environment-setup script is run at the end of my .bashrc file.
Running Eclipse from a shell known to "work" does indeed allow the cross compiler to run. When Eclipse is started using the Gnome launcher, it does not work..... - GG 01:50 PM Software Development: RE: Eclipse CDT Builder problem when set up for cross compile
- Hi Fred,
Where are you running the angstrom environment-setup script? We typically add this to the end of our bashrc and things work fine.
Also, how are you starting up Eclipse? Have you tried launching it from a terminal (where y... - Hi.
I am getting the following error when attempting to build a project in Eclipse. I am not using CL's VM - my Eclipse version is 3.5.2 running on Ubuntu, and the cross compiler tool chain was installed per the CL wiki:
**** Inter...
08/12/2011
- MW 07:07 AM FPGA Development: RE: 372 MHz
- Hi Rob,
In general, running at different EMIFA bus rates should be OK as long as you keep in mind the following points:
1) In general, it is best to configure your new frequency before loading your FPGA. If the FPGA is using a DCM...
08/11/2011
- TI 06:23 PM Software Development: RE: git connection
- Thomas
We were having some issues with our server earlier today. It should be all better now.
cheers
/Tim - Hi,
How are you doing ?
I was following the steps listed here:
http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Build_VM
but had problems with step 7. The git connection gets refused. The port 9418 is open.... - Hello,
I am running my L138 CPU at 372 MHz, which results in the EMIFA bus running at 93MHz instead of 100 MHZ.
I reused Critical Link supplied VHDL code for the EMIFA bus core. Are there any changes needed in this core to accommo...
08/09/2011
- ML 03:38 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- It worked! I changed to 0x40 and used 16 bit numbers. Here's the new code that worked-
UInt32 *Fpga_mem_ptr = (unsigned int *)0x66000040; //use CS5
UInt16 Fpga_mem_write = 0x45678932;
UInt16 Fpga_mem_read;
*Fpga_mem_ptr = Fpga_... - MW 02:30 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Well, OK.
If you are using our framework with the base module, the address at offset zero corresponds to a read only register.
Try offset 0x40, which corresponds to a scratch RAM we implemented in the FPGA. You should also (though... - ML 02:09 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- I tried to use the following code to write and read from a register. I used both CS4 and CS5 (0x64000000 and 0x66000000 respectively)
UInt32 *Fpga_mem_ptr = (unsigned int *)0x64000000;
UInt32 Fpga_mem_write = 0x45678932; ... - ML 12:19 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Well the wiki says CS5 is used for the DSP, but when I look at the VHDL it says CS4.
- MW 12:15 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Marc,
Are you using CS4 or CS5?
0x66000000 corresponds to CS5.
-Mike
- ML 12:04 PM Software Development: RE: Using the EMIFA to read/write FPGA registers
- So does the EMIFA just run in the background and constantly refresh the values? Or does it perform an action when you go to read a value from DSP memory?
- GG 11:55 AM Software Development: RE: Using the EMIFA to read/write FPGA registers
- Hi Marc,
The FPGA registers are memory mapped starting at DSP address 0x66000000. The registers for each additional core start at subsequent offsets of 0x80.
\Greg - Hey All,
I am trying to access the FPGA registers using the EMIFA, but I am having trouble finding documentation explaining the basics of how to tell the EMIFA to read a register in the FPGA. I'm using the DSP core of the OMAPL138, w... - CM 03:36 PM Software Development: RE: continual reboot
- @sfh_OMAP-L138 -erase -p COM7@ worked!!
- MW 03:00 PM Software Development: RE: continual reboot
- Should. You'll need to reflash again the u-Boot and UBL. Give it a try. (good catch, BTW).
-Mike
- CM 02:49 PM Software Development: RE: continual reboot
- Would this work?
sfh_OMAP-L138 -erase
help sez:
Global erase of the flash memory device (no input files) - MW 02:46 PM Software Development: RE: continual reboot
- Argh. The SPI reprogramming doesn't wipe the u-Boot environment or the FPGA environment, so it just picks back up where it left off. I think we need to update the flashing utility to wipe the u-Boot environment and/or the FLASH environ...
- CM 02:41 PM Software Development: RE: continual reboot
- Control-C does not work. Tried in both HyperTerminal and Putty.
Also tried dead board instructions with seemingly successful results but still got the autoboot loop:
(AIS Parse): BOOTME received!
(AIS Parse): Performing Start-Word... - MW 02:33 PM Software Development: RE: continual reboot
- Try hitting control-C continuously while booting. If that does not work, you can use the "programming a dead board" technique using the UART loader to reflash the SPI from the ground up. I think that control-C should work for you, thou...
- Hi,
I modified the FPGA code and during the write the board rebooted.
I had bootfpga set to load the fpga automatically on boot so now I'm stuck.
How do I break this infinite reboot loop?
HyperTerminal session looks like this:
...
08/08/2011
- GG 10:59 AM Software Development: RE: Mounting USB Flash Memory (mitydspl138)
- Hi Fred,
Most likely the *USB Mass Storage support* option is not selected in the config for the kernel you're using.
Once this is enabled the USB flash drive should be automatically mounted to a directory in /media/ when it's plug...
08/05/2011
- I have the mitydspl138, baseboard, and the standard Critical Link Linux kernel. When I plug a usb flash drive into the type A slot, I get a log message:
usb 1-1: new full speed USB device using ohci and address 18
However, it does ...
08/03/2011
- MW 10:17 AM FPGA Development: RE: Programming the FPGA
- The pwm.ngc should be included in the 2011-08-01 MDK release (just published).
-Mike
- CM 09:41 AM FPGA Development: RE: Programming the FPGA
- I successfully built this project but I had to comment out anything related to pwm. Seems I do not have the pwm.ngc netlist file. Also generated the correct .bin file same as what you guys provided.
07/29/2011
- CM 11:37 AM FPGA Development: RE: Programming the FPGA
- Thanks Mike. I picked up the common VHDL files with no trouble.
However, when I tried to add a netlist file (.ngc?), I got an error that indicates a different FPGA than I have (for which the project was built).
How can I get the co... - MW 07:30 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Yeah, the Xilinx ISE file format really doesn't use relative path names very well.
As far as the VHDL, all of the common/base VHDL needed to build the top level (EMIF interface, the base module, the core_version module, e...
07/27/2011
- MW 05:28 PM Software Development: RE: NAND controller, EDMA3 and EMIFA priorities
- Hi Mads,
I'm not sure there is much more you can do than what is already configured.
You might consider cross posting this over on "TI's E2E site":http://e2e.ti.com/?DCMP=E2E_E2E_E2E&CMP=KNC-GoogleTI&247SEM, as this is sort of a ge... - Hi
I have a few questions regarding the NAND flash and EMIFA.
From the EDMA priority settings below (which I just dumped directly from the registers)
MSTPRI0 = 0x44442222
MSTPRI1 = 0x44440000
MSTPRI2 = 0x54604404
It seems EDM... - MC 05:05 PM Software Development: RE: Mapping code to IRAM
- Hi Mark
You could try the #pragma CODE_SECTION(<function name>, "mysect") (In C++ you omit the function name and places the pragma before the declaration). You will probably have to define your own section in the CMD file.
Look at ...
07/26/2011
- TC 05:14 PM Software Development: RE: Mapping code to IRAM
- Hi Marc -
I'm not sure we will have the answer to this question as it's really a TI question. While we're waiting for a response from my team you may also wish to post it on the TI e2e forums.
Tom - Hey All,
I am using CCS4 and SYS/BIOS to program the DSP core in the L138, and I am trying to figure out how to specify the linker option so that a certain C function gets mapped into IRAM, instead of DDR. When I look at the C/C++ Bui... - CM 09:43 AM FPGA Development: RE: Programming the FPGA
- I opened this project file in XISE and it yelled at me for a number of VHD files (see attached png).
example.zip - XISE project and source for IndustrialIO.bin - LX45 Industrial IO Board FPGA (no display support) (60.1 KB)
Is this ...
07/24/2011
- CM 08:44 PM FPGA Development: RE: Programming the FPGA
- Success has been achieved. Thanks Mike!
I loaded the stock uImage from the .run file supplied with the kit. That did the trick - I can now startup the board, it flushes and then automatically loads the FPGA during boot all the way to ... - MW 12:55 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I think you need to modify the bootargs assuming the NAND has a valid filesystem on it.
See "this wiki page":http://support.criticallink.com/redmine/projects/arm9-platforms/wiki/Linux_Root_File_System.
Specifically, yo... - CM 09:45 AM FPGA Development: RE: Programming the FPGA
- The uImage_Indio_20110723 kernel image booted but could not mount to a filesystem.
Getting closer!
I attached the full bootlog.
07/23/2011
- CM 12:52 PM FPGA Development: RE: Programming the FPGA
- Thanks Mike.
My plan is to also extract the image from the .run file and try both this afternoon.
I am using the Industrial I/O baseboard.
I would also be interested in building an image from source. As you indicated yesterday t... - MW 11:40 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I am attaching a uImage file built for the Industrial I/O board from our kernel code baseline.
This really should work for your set up, assuming you are using an Industrial I/O baseboard.
Your steps should also get you... - CM 10:57 AM FPGA Development: RE: Programming the FPGA
- Hey Mike,
Late yesterday I booted into UBOOT; cleared the bootfpga (setenv bootfpga;saveenv); rebooted with Angstrom image and still got stuck at "Starting kernel..."
I tried twice just to make sure I did NOT get FPGA DONE LED.
... - MW 09:04 AM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Just following up. Are you still DOA? Or did not programming the FPGA clear the issue?
-Mike
07/22/2011
- CM 01:24 PM FPGA Development: RE: Programming the FPGA
- Good point. I'll defer any FPGA programming until I resolve the linux kernel load.
Here's the boot text. You can see the auto FPGA programming in the text. I'll turn that off and try again,
OMAP-L138/AM-1808/AM-1810 initialization ... - MW 01:14 PM FPGA Development: RE: Programming the FPGA
- Also,
Can you dump the entire boot text from power up to hang? Would like to see all the commands executed by the bootloader.
-Mike
- MW 01:13 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
Are you programming the FPGA before you load the kernel? The FPGA can cause problems with the kernel load if you are driving unused pins that might be tied to interrupt lines or NMI lines.
You may need to build that late... - CM 01:06 PM FPGA Development: RE: Programming the FPGA
- I tried again in case I screwed up the first time.
I also tried the uImage file in /boot on another of our boards. That image got stuck in the same way.
From files area: Linux-2.6.34-rc1-07430-g2e70fb6
From another of our dev kits...
07/21/2011
- CM 05:00 PM FPGA Development: RE: Programming the FPGA
- Hi Greg,
Thanks for XISE files.
I followed instructions from Linux Kernel installtion using uImage from files area and the boot gets stuck as shown below (starting kernel). Maybe I need the uImage file that came preloaded on the bo... - GG 02:03 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
I've attached the project file used to build the .bin file I posted earlier. You'll need to link against our cores in order to build this project, and those can be found in the latest MDK release.
\Greg - CM 02:02 PM FPGA Development: RE: Programming the FPGA
- The revised read instruction works!
We have the L138-FI-225-RC. My mistake. I was looking at the wrong line in the orderable section in the L138 SOM spec.
Thanks for all your support in our "startup" activities. In me you are deali... - MW 01:43 PM FPGA Development: RE: Programming the FPGA
- Hi Craig,
For the bootgpga image, you need to read out all of the image into RAM before trying to program the FPGA.
I think you need to change: - CM 01:03 PM FPGA Development: RE: Programming the FPGA
- Question on automatically loading the FPGA at boot...
I've followed these instructions:
loadb 0xC0700000
[send the correct IndustrialIO.bin using kermit]
sf probe 0
sf erase 0x580000 0x170000
sf write 0xC0700000 0x580000 ${fi... - CM 12:21 PM FPGA Development: RE: Programming the FPGA
- Can you guys zip up and post or e-mail me source files used to generate this .bin?
I would like to play some with the FPGA.
IndustrialIO.bin - LX45 Industrial IO Board FPGA (no display support) (1.4 MB) - CM 11:09 AM FPGA Development: RE: Programming the FPGA
- Hi Tim.
I'm on my 3rd USB-to-serial adapter and 4th attempt at driver update. I'm sure some manager got a nice bonus for taking cost out of these adaptors.
I've finally programmed the flash. The board now boots to U-BOOT with no pr... - CM 10:15 AM FPGA Development: RE: Programming the FPGA
- Hi Tim,
Do I need a different version of SPIWriter_MityDSP-L138.out? Didn't see this file in the latest zip.
I tried this latest version of the utility with these results. A little different - also read error prior to BOOTME receiv... - TI 09:07 AM FPGA Development: RE: Programming the FPGA
- Craig
I have uploaded the latest serial programming utility to the files section.
Try that and see if it corrects your timeout issue.
cheers
/Tim - CM 08:22 AM FPGA Development: RE: Programming the FPGA
- I've tried several other usb to serial adaptors with no luck.
I get the same error:
(AIS Parse): Performing Opcode Sync...
(Serial Port): Read error! (The operation has timed out.)
(AIS Parse): I/O Error in read!
Do I have the ...