Bob,
The Terasic loopback card just connects the HSMC TX pins to the RX pins. It has no active parts, so the speed limit comes from the Cyclone V FPGA on the module and the signal path, not from anything on the card or our baseboard.
This assumes the card is on the Full HSMC connector (J300). There, the HSMC1 TX/RX pairs run at 2.5V and go to the FPGA's dedicated LVDS transmitter and receiver pins. On the Partial HSMC connector (J301), TX6/RX6 go through 0 ohm resistors that are not fitted on a standard dev board, so the loopback won't work there.
- 2.5V single-ended at 166 MHz (TX6 to RX6): Yes, that is well within what the Cyclone V I/O can do. You still need to close timing in Quartus, and since the signal passes through two HSMC connectors, pick a suitable drive strength and slew rate.
- LVDS: Yes. Your 5CSX-H6-4YA-RI uses an I7 speed grade FPGA, which supports true LVDS up to 740 Mbps transmit and 840 Mbps receive (using the SERDES), as long as your design meets timing. There is no LVDS termination on the card or the baseboard, so turn on the FPGA's on-chip differential termination on the RX pins.
The full numbers are in Table 34, "High-Speed I/O Specifications for Cyclone V Devices", of the Cyclone V Device Datasheet:
https://www.intel.com/content/www/us/en/docs/programmable/683801.html
- Mike
