RE: Flat Device Tree source file configuration for 512MB ... ยป commit-299d705.patch
| arch/arm/boot/dts/am335x-mitysom.dts | ||
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>;
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};
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/* nandflash_pins_default: nandflash_pins_default { */
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/* pinctrl-single,pins = < */
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/* 0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad0.gpmc_ad0 *\/ */
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/* 0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad1.gpmc_ad1 *\/ */
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/* 0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad2.gpmc_ad2 *\/ */
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/* 0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad3.gpmc_ad3 *\/ */
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/* 0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad4.gpmc_ad4 *\/ */
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/* 0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad5.gpmc_ad5 *\/ */
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/* 0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad6.gpmc_ad6 *\/ */
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/* 0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_ad7.gpmc_ad7 *\/ */
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/* 0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /\* gpmc_wait0.gpmc_wait0 *\/ */
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/* 0x074 (PIN_INPUT_PULLUP | MUX_MODE7) /\* gpmc_wpn.gpio0_30 *\/ */
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/* 0x07c (PIN_OUTPUT | MUX_MODE0) /\* gpmc_csn0.gpmc_csn0 *\/ */
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/* 0x090 (PIN_OUTPUT | MUX_MODE0) /\* gpmc_advn_ale.gpmc_advn_ale *\/ */
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/* 0x094 (PIN_OUTPUT | MUX_MODE0) /\* gpmc_oen_ren.gpmc_oen_ren *\/ */
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/* 0x098 (PIN_OUTPUT | MUX_MODE0) /\* gpmc_wen.gpmc_wen *\/ */
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/* 0x09c (PIN_OUTPUT | MUX_MODE0) /\* gpmc_be0n_cle.gpmc_be0n_cle *\/ */
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/* >; */
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/* }; */
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/* RAD - Updated for MitySOM-335x */
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nandflash_pins_default: nandflash_pins_default {
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pinctrl-single,pins = <
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0x000 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x004 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x008 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0x00c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x010 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x014 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x018 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x01c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x070 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x074 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wpn.gpmc_wpn */
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0x07c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x090 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x094 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x098 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x09c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0_cle.gpmc_be0_cle */
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>;
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};
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/* nandflash_pins_sleep: nandflash_pins_sleep { */
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/* pinctrl-single,pins = < */
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/* 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0xc (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
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/* >; */
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/* }; */
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/* RAD - Updated for MitySOM-335x */
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nandflash_pins_sleep: nandflash_pins_sleep {
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pinctrl-single,pins = <
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0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
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0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
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>;
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};
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/* ecap0_pins_default: backlight_pins { */
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/* pinctrl-single,pins = < */
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| ... | ... | |
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*/
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/* &gpmc { */
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/* status = "okay"; */
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/* pinctrl-names = "default", "sleep"; */
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/* pinctrl-0 = <&nandflash_pins_default>; */
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/* pinctrl-1 = <&nandflash_pins_sleep>; */
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/* ranges = <0 0 0x08000000 0x10000000>; /\* CS0: NAND *\/ */
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/* nand@0,0 { */
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/* reg = <0 0 0>; /\* CS0, offset 0 *\/ */
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/* ti,nand-ecc-opt = "bch8"; */
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/* ti,elm-id = <&elm>; */
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/* nand-bus-width = <8>; */
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/* gpmc,device-width = <1>; */
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/* gpmc,sync-clk-ps = <0>; */
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/* gpmc,cs-on-ns = <0>; */
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/* gpmc,cs-rd-off-ns = <44>; */
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/* gpmc,cs-wr-off-ns = <44>; */
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/* gpmc,adv-on-ns = <6>; */
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/* gpmc,adv-rd-off-ns = <34>; */
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/* gpmc,adv-wr-off-ns = <44>; */
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/* gpmc,we-on-ns = <0>; */
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/* gpmc,we-off-ns = <40>; */
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/* gpmc,oe-on-ns = <0>; */
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/* gpmc,oe-off-ns = <54>; */
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/* gpmc,access-ns = <64>; */
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/* gpmc,rd-cycle-ns = <82>; */
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/* gpmc,wr-cycle-ns = <82>; */
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/* gpmc,wait-on-read = "true"; */
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/* gpmc,wait-on-write = "true"; */
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/* gpmc,bus-turnaround-ns = <0>; */
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/* gpmc,cycle2cycle-delay-ns = <0>; */
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/* gpmc,clk-activation-ns = <0>; */
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/* gpmc,wait-monitoring-ns = <0>; */
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/* gpmc,wr-access-ns = <40>; */
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/* gpmc,wr-data-mux-bus-ns = <0>; */
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/* /\* MTD partition table *\/ */
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/* /\* All SPL-* partitions are sized to minimal length */
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/* * which can be independently programmable. For */
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/* * NAND flash this is equal to size of erase-block *\/ */
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/* #address-cells = <1>; */
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/* #size-cells = <1>; */
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/* partition@0 { */
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/* label = "NAND.SPL"; */
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/* reg = <0x00000000 0x000020000>; */
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/* }; */
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/* partition@1 { */
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/* label = "NAND.SPL.backup1"; */
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/* reg = <0x00020000 0x00020000>; */
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/* }; */
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/* partition@2 { */
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/* label = "NAND.SPL.backup2"; */
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/* reg = <0x00040000 0x00020000>; */
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/* }; */
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/* partition@3 { */
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/* label = "NAND.SPL.backup3"; */
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/* reg = <0x00060000 0x00020000>; */
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/* }; */
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/* partition@4 { */
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/* label = "NAND.u-boot-spl-os"; */
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/* reg = <0x00080000 0x00040000>; */
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/* }; */
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/* partition@5 { */
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/* label = "NAND.u-boot"; */
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/* reg = <0x000C0000 0x00100000>; */
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/* }; */
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/* partition@6 { */
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/* label = "NAND.u-boot-env"; */
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/* reg = <0x001C0000 0x00020000>; */
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/* }; */
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/* partition@7 { */
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/* label = "NAND.u-boot-env.backup1"; */
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/* reg = <0x001E0000 0x00020000>; */
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/* }; */
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/* partition@8 { */
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/* label = "NAND.kernel"; */
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/* reg = <0x00200000 0x00800000>; */
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/* }; */
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/* partition@9 { */
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/* label = "NAND.file-system"; */
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/* reg = <0x00A00000 0x0F600000>; */
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/* }; */
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/* }; */
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/* }; */
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&gpmc {
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status = "okay";
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&nandflash_pins_default>;
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pinctrl-1 = <&nandflash_pins_sleep>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0: 256 MB NAND */
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nand@0,0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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ti,nand-ecc-opt = "bch8"; /* from baseboard file */
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>; /* from baseboard file */
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gpmc,cs-rd-off-ns = <44>; /* from baseboard file */
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gpmc,cs-wr-off-ns = <44>; /* from baseboard file */
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gpmc,adv-on-ns = <6>; /* from baseboard file */
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gpmc,adv-rd-off-ns = <34>; /* from baseboard file */
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gpmc,adv-wr-off-ns = <44>; /* from baseboard file */
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gpmc,we-on-ns = <0>;
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gpmc,we-off-ns = <40>; /* from baseboard file */
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gpmc,oe-on-ns = <0>;
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gpmc,oe-off-ns = <54>; /* from baseboard file */
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gpmc,access-ns = <64>; /* from baseboard file */
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gpmc,rd-cycle-ns = <82>; /* from baseboard file */
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gpmc,wr-cycle-ns = <82>; /* from baseboard file */
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>; /* from baseboard file */
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x000020000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x00020000 0x00020000>;
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};
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partition@2 {
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label = "NAND.SPL.backup2";
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reg = <0x00040000 0x00020000>;
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};
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partition@3 {
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label = "NAND.SPL.backup3";
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reg = <0x00060000 0x00020000>;
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};
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partition@4 {
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label = "NAND.u-boot";
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reg = <0x00080000 0x001E0000>;
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};
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partition@5 {
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label = "NAND.u-boot-env";
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reg = <0x00260000 0x00020000>;
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};
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partition@6 {
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label = "NAND.kernel";
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reg = <0x00280000 0x00500000>;
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};
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partition@7 {
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label = "NAND.file-system";
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reg = <0x00780000 0x0F880000>;
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};
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};
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};
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