commit 299d70542d4f63ea69d34e99b0e8f2172b634ad3
Author: Bob Duke <bduke@criticallink.com>
Date:   Thu May 7 22:37:42 2015 +0000

    ARM: MitySOM: Add device tree support for 256MB NAND

diff --git a/arch/arm/boot/dts/am335x-mitysom.dts b/arch/arm/boot/dts/am335x-mitysom.dts
index 4594547..77e4721 100644
--- a/arch/arm/boot/dts/am335x-mitysom.dts
+++ b/arch/arm/boot/dts/am335x-mitysom.dts
@@ -176,45 +176,47 @@
 		>;
 	};
 
-	/* nandflash_pins_default: nandflash_pins_default { */
-	/*	pinctrl-single,pins = < */
-	/*		0x000 (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad0.gpmc_ad0 *\/ */
-	/*		0x004 (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad1.gpmc_ad1 *\/ */
-	/*		0x008 (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad2.gpmc_ad2 *\/ */
-	/*		0x00c (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad3.gpmc_ad3 *\/ */
-	/*		0x010 (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad4.gpmc_ad4 *\/ */
-	/*		0x014 (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad5.gpmc_ad5 *\/ */
-	/*		0x018 (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad6.gpmc_ad6 *\/ */
-	/*		0x01c (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_ad7.gpmc_ad7 *\/ */
-	/*		0x070 (PIN_INPUT_PULLUP | MUX_MODE0)	/\* gpmc_wait0.gpmc_wait0 *\/ */
-	/*		0x074 (PIN_INPUT_PULLUP | MUX_MODE7)	/\* gpmc_wpn.gpio0_30 *\/ */
-	/*		0x07c (PIN_OUTPUT | MUX_MODE0)		/\* gpmc_csn0.gpmc_csn0  *\/ */
-	/*		0x090 (PIN_OUTPUT | MUX_MODE0)		/\* gpmc_advn_ale.gpmc_advn_ale *\/ */
-	/*		0x094 (PIN_OUTPUT | MUX_MODE0)		/\* gpmc_oen_ren.gpmc_oen_ren *\/ */
-	/*		0x098 (PIN_OUTPUT | MUX_MODE0)		/\* gpmc_wen.gpmc_wen *\/ */
-	/*		0x09c (PIN_OUTPUT | MUX_MODE0)		/\* gpmc_be0n_cle.gpmc_be0n_cle *\/ */
-	/*	>; */
-	/* }; */
+	/* RAD - Updated for MitySOM-335x */
+	nandflash_pins_default: nandflash_pins_default {
+		pinctrl-single,pins = <
+			0x000 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
+			0x004 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
+			0x008 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
+			0x00c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
+			0x010 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
+			0x014 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
+			0x018 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
+			0x01c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
+			0x070 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			0x074 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wpn.gpmc_wpn */
+			0x07c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0  */
+			0x090 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
+			0x094 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
+			0x098 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
+			0x09c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0_cle.gpmc_be0_cle */
+		>;
+	};
 
-	/* nandflash_pins_sleep: nandflash_pins_sleep { */
-	/*	pinctrl-single,pins = < */
-	/*		0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0xc (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*		0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) */
-	/*	>; */
-	/* }; */
+	/* RAD - Updated for MitySOM-335x */
+	nandflash_pins_sleep: nandflash_pins_sleep {
+		pinctrl-single,pins = <
+			0x0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0xc (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+			0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+		>;
+	};
 
 	/* ecap0_pins_default: backlight_pins { */
 	/*	pinctrl-single,pins = < */
@@ -516,88 +518,80 @@
 */
 
 
-/* &gpmc { */
-/*	status = "okay"; */
-/*	pinctrl-names = "default", "sleep"; */
-/*	pinctrl-0 = <&nandflash_pins_default>; */
-/*	pinctrl-1 = <&nandflash_pins_sleep>; */
-/*	ranges = <0 0 0x08000000 0x10000000>;	/\* CS0: NAND *\/ */
-/*	nand@0,0 { */
-/*		reg = <0 0 0>; /\* CS0, offset 0 *\/ */
-/*		ti,nand-ecc-opt = "bch8"; */
-/*		ti,elm-id = <&elm>; */
-/*		nand-bus-width = <8>; */
-/*		gpmc,device-width = <1>; */
-/*		gpmc,sync-clk-ps = <0>; */
-/*		gpmc,cs-on-ns = <0>; */
-/*		gpmc,cs-rd-off-ns = <44>; */
-/*		gpmc,cs-wr-off-ns = <44>; */
-/*		gpmc,adv-on-ns = <6>; */
-/*		gpmc,adv-rd-off-ns = <34>; */
-/*		gpmc,adv-wr-off-ns = <44>; */
-/*		gpmc,we-on-ns = <0>; */
-/*		gpmc,we-off-ns = <40>; */
-/*		gpmc,oe-on-ns = <0>; */
-/*		gpmc,oe-off-ns = <54>; */
-/*		gpmc,access-ns = <64>; */
-/*		gpmc,rd-cycle-ns = <82>; */
-/*		gpmc,wr-cycle-ns = <82>; */
-/*		gpmc,wait-on-read = "true"; */
-/*		gpmc,wait-on-write = "true"; */
-/*		gpmc,bus-turnaround-ns = <0>; */
-/*		gpmc,cycle2cycle-delay-ns = <0>; */
-/*		gpmc,clk-activation-ns = <0>; */
-/*		gpmc,wait-monitoring-ns = <0>; */
-/*		gpmc,wr-access-ns = <40>; */
-/*		gpmc,wr-data-mux-bus-ns = <0>; */
-/*		/\* MTD partition table *\/ */
-/*		/\* All SPL-* partitions are sized to minimal length */
-/*		 * which can be independently programmable. For */
-/*		 * NAND flash this is equal to size of erase-block *\/ */
-/*		#address-cells = <1>; */
-/*		#size-cells = <1>; */
-/*		partition@0 { */
-/*			label = "NAND.SPL"; */
-/*			reg = <0x00000000 0x000020000>; */
-/*		}; */
-/*		partition@1 { */
-/*			label = "NAND.SPL.backup1"; */
-/*			reg = <0x00020000 0x00020000>; */
-/*		}; */
-/*		partition@2 { */
-/*			label = "NAND.SPL.backup2"; */
-/*			reg = <0x00040000 0x00020000>; */
-/*		}; */
-/*		partition@3 { */
-/*			label = "NAND.SPL.backup3"; */
-/*			reg = <0x00060000 0x00020000>; */
-/*		}; */
-/*		partition@4 { */
-/*			label = "NAND.u-boot-spl-os"; */
-/*			reg = <0x00080000 0x00040000>; */
-/*		}; */
-/*		partition@5 { */
-/*			label = "NAND.u-boot"; */
-/*			reg = <0x000C0000 0x00100000>; */
-/*		}; */
-/*		partition@6 { */
-/*			label = "NAND.u-boot-env"; */
-/*			reg = <0x001C0000 0x00020000>; */
-/*		}; */
-/*		partition@7 { */
-/*			label = "NAND.u-boot-env.backup1"; */
-/*			reg = <0x001E0000 0x00020000>; */
-/*		}; */
-/*		partition@8 { */
-/*			label = "NAND.kernel"; */
-/*			reg = <0x00200000 0x00800000>; */
-/*		}; */
-/*		partition@9 { */
-/*			label = "NAND.file-system"; */
-/*			reg = <0x00A00000 0x0F600000>; */
-/*		}; */
-/*	}; */
-/* }; */
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&nandflash_pins_default>;
+	pinctrl-1 = <&nandflash_pins_sleep>;
+	ranges = <0 0 0x08000000 0x10000000>;	/* CS0: 256 MB NAND */
+	nand@0,0 {
+		reg = <0 0 0>; /* CS0, offset 0 */
+		ti,nand-ecc-opt = "bch8";	/* from baseboard file */
+		ti,elm-id = <&elm>;
+		nand-bus-width = <8>;
+		gpmc,device-width = <1>;
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>; 		/* from baseboard file */
+		gpmc,cs-rd-off-ns = <44>; 	/* from baseboard file */
+		gpmc,cs-wr-off-ns = <44>; 	/* from baseboard file */
+		gpmc,adv-on-ns = <6>; 		/* from baseboard file */
+		gpmc,adv-rd-off-ns = <34>; 	/* from baseboard file */
+		gpmc,adv-wr-off-ns = <44>; 	/* from baseboard file */
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <40>; 		/* from baseboard file */
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <54>; 		/* from baseboard file */
+		gpmc,access-ns = <64>; 		/* from baseboard file */
+		gpmc,rd-cycle-ns = <82>; 	/* from baseboard file */
+		gpmc,wr-cycle-ns = <82>; 	/* from baseboard file */
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+		gpmc,wr-access-ns = <40>; 	/* from baseboard file */
+		gpmc,wr-data-mux-bus-ns = <0>;
+		/* MTD partition table */
+		/* All SPL-* partitions are sized to minimal length
+		 * which can be independently programmable. For
+		 * NAND flash this is equal to size of erase-block */
+		#address-cells = <1>;
+		#size-cells = <1>;
+		partition@0 {
+			label = "NAND.SPL";
+			reg = <0x00000000 0x000020000>;
+		};
+		partition@1 {
+			label = "NAND.SPL.backup1";
+			reg = <0x00020000 0x00020000>;
+		};
+		partition@2 {
+			label = "NAND.SPL.backup2";
+			reg = <0x00040000 0x00020000>;
+		};
+		partition@3 {
+			label = "NAND.SPL.backup3";
+			reg = <0x00060000 0x00020000>;
+		};
+		partition@4 {
+			label = "NAND.u-boot";
+			reg = <0x00080000 0x001E0000>;
+		};
+		partition@5 {
+			label = "NAND.u-boot-env";
+			reg = <0x00260000 0x00020000>;
+		};
+		partition@6 {
+			label = "NAND.kernel";
+			reg = <0x00280000 0x00500000>;
+		};
+		partition@7 {
+			label = "NAND.file-system";
+			reg = <0x00780000 0x0F880000>;
+		};
+	};
+};
 
 
 
