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Output of u-boot with my complied sd card image:
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U-Boot SPL 2023.07-rc6-ge64596af4c-dirty (Oct 20 2025 - 21:45:58 -0400)
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DDRCAL: Scrubbing ECC RAM (1024 MiB).
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DDRCAL: SDRAM-ECC initialized success with 608 ms
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MPU 800000 kHz
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DDR 400000 kHz
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EOSC1 25000 kHz
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EOSC2 25000 kHz
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F2S_SDR_REF 0 kHz
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F2S_PER_REF 0 kHz
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MMC 50000 kHz
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QSPI 400000 kHz
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UART 100000 kHz
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SPI 200000 kHz
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Trying to boot from MMC1
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U-Boot 2023.07-rc6-ge64596af4c-dirty (Oct 20 2025 - 21:45:58 -0400) Critical Link MitySOM-5CSx
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CPU: Altera SoCFPGA Platform
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FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0
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BOOT: SD/MMC Internal Transceiver (3.0V)
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DRAM: 1 GiB
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Core: 35 devices, 19 uclasses, devicetree: separate
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MMC: dwmmc0@ff704000: 0
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Loading Environment from MMC... OK
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In: serial
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Out: serial
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Err: serial
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Model: MitySOM-5CSX-H6-42A Altera SOCFPGA Cyclone V
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BOARD: Critical Link MitySOM-5CSx Module
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Net: eth0: ethernet@ff702000
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gpio: pin 0 (gpio 0) value is 1
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Hit any key to stop autoboot: 0
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MitySOM-5CSx #
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output of u-boot with the provided sd card image.
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U-Boot SPL 2013.01.01 (Oct 19 2023 - 21:49:03)
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BOARD : Critical Link MitySOM-5CSx Module
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CLOCK: EOSC1 clock 25000 KHz
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CLOCK: EOSC2 clock 25000 KHz
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CLOCK: F2S_SDR_REF clock 0 KHz
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CLOCK: F2S_PER_REF clock 0 KHz
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CLOCK: MPU clock 800 MHz
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CLOCK: DDR clock 400 MHz
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CLOCK: UART clock 100000 KHz
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CLOCK: MMC clock 50000 KHz
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CLOCK: QSPI clock 400000 KHz
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RESET: COLD
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SDRAM: Initializing MMR registers
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SDRAM: Calibrating PHY
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SEQ.C: Preparing to start memory calibration
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SEQ.C: CALIBRATION PASSED
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SDRAM: 1024 MiB
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SDRAM: Initializing SDRAM ECC
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SDRAM: ECC initialized successfully with 1511 ms
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SDRAM: ECC Enabled
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ALTERA DWMMC: 0
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U-Boot 2013.01.01 (Oct 19 2023 - 21:49:22) Critical Link MitySOM-5CSx
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CPU : Altera SOCFPGA Platform
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BOARD : Critical Link MitySOM-5CSx Module
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I2C: ready
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DRAM: 1 GiB
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MMC: ALTERA DWMMC: 0
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In: serial
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Out: serial
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Err: serial
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Net: mii0
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gpio: pin 0 (bank/mask = 0/0x00000001)
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gpio: pin 0 (gpio 0) value is 1
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Hit any key to stop autoboot: 0
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MitySOM-5CSx #
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