Output of u-boot with my complied sd card image: U-Boot SPL 2023.07-rc6-ge64596af4c-dirty (Oct 20 2025 - 21:45:58 -0400) DDRCAL: Scrubbing ECC RAM (1024 MiB). DDRCAL: SDRAM-ECC initialized success with 608 ms MPU 800000 kHz DDR 400000 kHz EOSC1 25000 kHz EOSC2 25000 kHz F2S_SDR_REF 0 kHz F2S_PER_REF 0 kHz MMC 50000 kHz QSPI 400000 kHz UART 100000 kHz SPI 200000 kHz Trying to boot from MMC1 U-Boot 2023.07-rc6-ge64596af4c-dirty (Oct 20 2025 - 21:45:58 -0400) Critical Link MitySOM-5CSx CPU: Altera SoCFPGA Platform FPGA: Altera Cyclone V, SE/A6 or SX/C6 or ST/D6, version 0x0 BOOT: SD/MMC Internal Transceiver (3.0V) DRAM: 1 GiB Core: 35 devices, 19 uclasses, devicetree: separate MMC: dwmmc0@ff704000: 0 Loading Environment from MMC... OK In: serial Out: serial Err: serial Model: MitySOM-5CSX-H6-42A Altera SOCFPGA Cyclone V BOARD: Critical Link MitySOM-5CSx Module Net: eth0: ethernet@ff702000 gpio: pin 0 (gpio 0) value is 1 Hit any key to stop autoboot: 0 MitySOM-5CSx # output of u-boot with the provided sd card image. U-Boot SPL 2013.01.01 (Oct 19 2023 - 21:49:03) BOARD : Critical Link MitySOM-5CSx Module CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 800 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 50000 KHz CLOCK: QSPI clock 400000 KHz RESET: COLD SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB SDRAM: Initializing SDRAM ECC SDRAM: ECC initialized successfully with 1511 ms SDRAM: ECC Enabled ALTERA DWMMC: 0 U-Boot 2013.01.01 (Oct 19 2023 - 21:49:22) Critical Link MitySOM-5CSx CPU : Altera SOCFPGA Platform BOARD : Critical Link MitySOM-5CSx Module I2C: ready DRAM: 1 GiB MMC: ALTERA DWMMC: 0 In: serial Out: serial Err: serial Net: mii0 gpio: pin 0 (bank/mask = 0/0x00000001) gpio: pin 0 (gpio 0) value is 1 Hit any key to stop autoboot: 0 MitySOM-5CSx #