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kanevsky@fpga-sm:~$ git clone -b pro_24.2_stable git://support.criticallink.com/home/git/mitysom-a5e-ref.git
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Cloning into 'mitysom-a5e-ref'...
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remote: Enumerating objects: 258, done.
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4
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remote: Counting objects: 100% (258/258), done.
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remote: Compressing objects: 100% (249/249), done.
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remote: Total 258 (delta 138), reused 0 (delta 0), pack-reused 0
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Receiving objects: 100% (258/258), 553.21 KiB | 2.14 MiB/s, done.
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8
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Resolving deltas: 100% (138/138), done.
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9
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kanevsky@fpga-sm:~$ ls
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fpga MCD4 mitysom-a5e-ref quartus.log quartus.rec snap
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kanevsky@fpga-sm:~$ cd mitysom-a5e-ref/
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.git/ mitysom-a5e-ref-base/ mitysom-a5e-ref-sdram/ mitysom-a5e-ref-sfp/
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kanevsky@fpga-sm:~$ cd mitysom-a5e-ref/mitysom-a5e-ref-base/
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kanevsky@fpga-sm:~/mitysom-a5e-ref/mitysom-a5e-ref-base$ make jic
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15
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Design config:
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AGILEX5_MODEL = mitysom
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PROJECT_NAME = a5e
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FPGA_EMIF = 0
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QSFP_EXAMPLE = 0
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SFP_EXAMPLE = 0
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SDRAM_EN = 0
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USB_EN = 1
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TEST_FIXTURE = 0
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24
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qsys-generate --quartus-project=a5e.qpf --clear-output-directory --rev=a5e a5e.qsys --upgrade-ip-cores
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***************************************************************
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Quartus is a registered trademark of Intel Corporation in the
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US and other countries. Portions of the Quartus Prime software
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code, and other portions of the code included in this download
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30
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or on this DVD, are licensed to Intel Corporation and are the
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copyrighted property of third parties. For license details,
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32
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refer to the End User License Agreement at
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http://fpgasoftware.intel.com/eula.
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34
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***************************************************************
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35
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36
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2025.08.29.13:55:31 Info: IP upgrade skipped for Platform Designer system /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys
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37
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2025.08.29.13:55:31 Info: Starting to upgrade the IP cores in the Platform Designer system
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38
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2025.08.29.13:55:31 Info: Finished upgrading the ip cores
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qsys-script --qpf=none --script=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/update_sysid.tcl --system-file=a5e.qsys
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40
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***************************************************************
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Quartus is a registered trademark of Intel Corporation in the
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US and other countries. Portions of the Quartus Prime software
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43
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code, and other portions of the code included in this download
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44
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or on this DVD, are licensed to Intel Corporation and are the
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45
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copyrighted property of third parties. For license details,
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46
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refer to the End User License Agreement at
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47
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http://fpgasoftware.intel.com/eula.
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48
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***************************************************************
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49
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50
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2025.08.29.13:55:31 Info: Doing: qsys-script --quartus-project=none --script=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/update_sysid.tcl --system-file=a5e.qsys
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51
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2025.08.29.13:55:37 Info: get_module_property FILE
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52
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2025.08.29.13:55:37 Info: get_instances
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53
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2025.08.29.13:55:37 Info: get_instance_property fabric_reset_bridge_0 CLASS_NAME
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54
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2025.08.29.13:55:37 Info: load_component fabric_reset_bridge_0
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55
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2025.08.29.13:55:37 Info: get_instantiation_property IP_FILE
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56
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2025.08.29.13:55:37 Info: get_component_property CLASS_NAME
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57
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2025.08.29.13:55:37 Info: get_instance_property gts_rst_seq_left CLASS_NAME
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58
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2025.08.29.13:55:37 Info: load_component gts_rst_seq_left
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59
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2025.08.29.13:55:39 Info: get_instantiation_property IP_FILE
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60
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2025.08.29.13:55:39 Info: get_component_property CLASS_NAME
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61
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2025.08.29.13:55:39 Info: get_instance_property hps_subsys CLASS_NAME
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62
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2025.08.29.13:55:39 Info: get_instance_property pio_inputs_0 CLASS_NAME
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63
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2025.08.29.13:55:39 Info: load_component pio_inputs_0
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64
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2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE
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65
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2025.08.29.13:55:40 Info: get_component_property CLASS_NAME
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66
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2025.08.29.13:55:40 Info: get_instance_property pio_outputs_0 CLASS_NAME
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67
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2025.08.29.13:55:40 Info: load_component pio_outputs_0
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68
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2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE
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69
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2025.08.29.13:55:40 Info: get_component_property CLASS_NAME
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70
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2025.08.29.13:55:40 Info: get_instance_property reset_release CLASS_NAME
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71
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2025.08.29.13:55:40 Info: load_component reset_release
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72
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2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE
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73
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2025.08.29.13:55:40 Info: get_component_property CLASS_NAME
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74
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2025.08.29.13:55:40 Info: get_instance_property sysid_qsys_0 CLASS_NAME
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75
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2025.08.29.13:55:40 Info: load_component sysid_qsys_0
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76
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2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE
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77
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2025.08.29.13:55:40 Info: get_component_property CLASS_NAME
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78
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2025.08.29.13:55:40 Info: load_system /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip
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79
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2025.08.29.13:55:40 Info: set_module_property GENERATION_ID 1756490137
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80
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2025.08.29.13:55:40 Info: validate_system
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81
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2025.08.29.13:55:40 Info: save_system /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip
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82
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qsys-generate --quartus-project=a5e.qpf --clear-output-directory --rev=a5e a5e.qsys --synthesis=VERILOG
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83
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***************************************************************
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84
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Quartus is a registered trademark of Intel Corporation in the
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US and other countries. Portions of the Quartus Prime software
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86
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code, and other portions of the code included in this download
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or on this DVD, are licensed to Intel Corporation and are the
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88
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copyrighted property of third parties. For license details,
|
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89
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refer to the End User License Agreement at
|
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http://fpgasoftware.intel.com/eula.
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91
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***************************************************************
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92
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93
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2025.08.29.13:55:45 Info: Parallel IP Generation is enabled.
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94
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2025.08.29.13:55:45 Info: Platform Designer will attempt to use 6 processors for parallel IP generation based on available number of processors and the total number of IP to be generated.
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95
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2025.08.29.13:55:45 Info:
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96
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2025.08.29.13:55:45 Info: Starting: Platform Designer system generation
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97
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2025.08.29.13:55:53 Info:
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98
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2025.08.29.13:55:53 Info: Generating on localhost:44239
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99
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0/hps_subsys_lwhps2fpga_mm_bridge_0_generation.rpt
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100
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
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101
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
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102
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
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103
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Transforming system: hps_subsys_lwhps2fpga_mm_bridge_0"
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104
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Naming system components in system: hps_subsys_lwhps2fpga_mm_bridge_0"
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105
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Processing generation queue"
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106
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Generating: hps_subsys_lwhps2fpga_mm_bridge_0"
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107
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Generating: hps_subsys_lwhps2fpga_mm_bridge_0_altera_avalon_mm_bridge_2010_tex5a4i"
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108
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: Done "hps_subsys_lwhps2fpga_mm_bridge_0" with 2 modules, 4 files
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109
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
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110
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2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip (hps_subsys_lwhps2fpga_mm_bridge_0) took 506 ms
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111
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2025.08.29.13:55:53 Info:
|
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112
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2025.08.29.13:55:53 Info: Generating on localhost:33047
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113
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0/a5e_pio_inputs_0_generation.rpt
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114
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
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115
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
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116
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
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117
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2025.08.29.13:55:53 Info: a5e_pio_inputs_0.pio_inputs_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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118
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2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Transforming system: a5e_pio_inputs_0"
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119
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2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Naming system components in system: a5e_pio_inputs_0"
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120
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2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Processing generation queue"
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121
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2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Generating: a5e_pio_inputs_0"
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122
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2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Generating: a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q"
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123
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2025.08.29.13:55:53 Info: pio_inputs_0: Starting RTL generation for module 'a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q'
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124
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2025.08.29.13:55:53 Info: pio_inputs_0: Generation command is [exec /opt/intelFPGA_pro/24.2/quartus/linux64//perl/bin/perl -I /opt/intelFPGA_pro/24.2/quartus/linux64//perl/lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/europa -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q --dir=/tmp/alt0329_13947256075190898555.dir/0001_pio_inputs_0_gen/ --quartus_dir=/opt/intelFPGA_pro/24.2/quartus --verilog --config=/tmp/alt0329_13947256075190898555.dir/0001_pio_inputs_0_gen//a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q_component_configuration.pl --do_build_sim=0 ]
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125
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2025.08.29.13:55:53 Info: pio_inputs_0: Done RTL generation for module 'a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q'
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126
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2025.08.29.13:55:53 Info: a5e_pio_inputs_0: Done "a5e_pio_inputs_0" with 2 modules, 2 files
|
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127
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
|
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128
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2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0.ip (a5e_pio_inputs_0) took 641 ms
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129
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2025.08.29.13:55:53 Info:
|
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130
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2025.08.29.13:55:53 Info: Generating on localhost:41175
|
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131
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0/a5e_pio_outputs_0_generation.rpt
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132
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
|
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133
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
|
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134
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
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135
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2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Transforming system: a5e_pio_outputs_0"
|
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136
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2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Naming system components in system: a5e_pio_outputs_0"
|
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137
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2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Processing generation queue"
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138
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2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Generating: a5e_pio_outputs_0"
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139
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2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Generating: a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma"
|
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140
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2025.08.29.13:55:53 Info: pio_outputs_0: Starting RTL generation for module 'a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma'
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141
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2025.08.29.13:55:53 Info: pio_outputs_0: Generation command is [exec /opt/intelFPGA_pro/24.2/quartus/linux64//perl/bin/perl -I /opt/intelFPGA_pro/24.2/quartus/linux64//perl/lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/europa -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma --dir=/tmp/alt0329_3243888775806564021.dir/0001_pio_outputs_0_gen/ --quartus_dir=/opt/intelFPGA_pro/24.2/quartus --verilog --config=/tmp/alt0329_3243888775806564021.dir/0001_pio_outputs_0_gen//a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma_component_configuration.pl --do_build_sim=0 ]
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142
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2025.08.29.13:55:53 Info: pio_outputs_0: Done RTL generation for module 'a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma'
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143
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2025.08.29.13:55:53 Info: a5e_pio_outputs_0: Done "a5e_pio_outputs_0" with 2 modules, 2 files
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144
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
|
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145
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2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0.ip (a5e_pio_outputs_0) took 530 ms
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146
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2025.08.29.13:55:53 Info:
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147
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2025.08.29.13:55:53 Info: Generating on localhost:44239
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148
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0/hps_subsys_lwhps2fpga_reset_bridge_0_generation.rpt
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149
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
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150
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
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151
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
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152
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Transforming system: hps_subsys_lwhps2fpga_reset_bridge_0"
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153
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Naming system components in system: hps_subsys_lwhps2fpga_reset_bridge_0"
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154
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Processing generation queue"
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155
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Generating: hps_subsys_lwhps2fpga_reset_bridge_0"
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156
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: Done "hps_subsys_lwhps2fpga_reset_bridge_0" with 1 modules, 1 files
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157
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
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158
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2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip (hps_subsys_lwhps2fpga_reset_bridge_0) took 62 ms
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159
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2025.08.29.13:55:53 Info:
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160
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2025.08.29.13:55:53 Info: Generating on localhost:41175
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161
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0/a5e_fabric_reset_bridge_0_generation.rpt
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162
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
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163
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
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164
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
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165
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2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Transforming system: a5e_fabric_reset_bridge_0"
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166
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2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Naming system components in system: a5e_fabric_reset_bridge_0"
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167
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2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Processing generation queue"
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168
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2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Generating: a5e_fabric_reset_bridge_0"
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169
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2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: Done "a5e_fabric_reset_bridge_0" with 1 modules, 1 files
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170
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
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171
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2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0.ip (a5e_fabric_reset_bridge_0) took 50 ms
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172
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2025.08.29.13:55:53 Info:
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173
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2025.08.29.13:55:53 Info: Generating on localhost:33047
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174
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0/a5e_sysid_qsys_0_generation.rpt
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175
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
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176
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
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177
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
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178
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0.sysid_qsys_0: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
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179
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0.sysid_qsys_0: Time stamp will be automatically updated when this component is generated.
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180
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Transforming system: a5e_sysid_qsys_0"
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181
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Naming system components in system: a5e_sysid_qsys_0"
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182
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Processing generation queue"
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183
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Generating: a5e_sysid_qsys_0"
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184
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Generating: altera_avalon_sysid_qsys"
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185
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2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: Done "a5e_sysid_qsys_0" with 2 modules, 2 files
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186
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
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187
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2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip (a5e_sysid_qsys_0) took 77 ms
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188
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2025.08.29.13:55:53 Info:
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189
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2025.08.29.13:55:53 Info: Generating on localhost:41175
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190
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0/hps_subsys_lwhps2fpga_clock_bridge_0_generation.rpt
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191
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
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192
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
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193
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
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194
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Transforming system: hps_subsys_lwhps2fpga_clock_bridge_0"
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195
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Naming system components in system: hps_subsys_lwhps2fpga_clock_bridge_0"
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196
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Processing generation queue"
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197
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Generating: hps_subsys_lwhps2fpga_clock_bridge_0"
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198
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2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: Done "hps_subsys_lwhps2fpga_clock_bridge_0" with 1 modules, 1 files
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199
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
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200
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2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip (hps_subsys_lwhps2fpga_clock_bridge_0) took 49 ms
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201
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2025.08.29.13:55:53 Info:
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202
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2025.08.29.13:55:53 Info: Generating on localhost:33047
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203
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2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release/a5e_reset_release_generation.rpt
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204
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2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40
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205
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2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis
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206
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2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release --family="Agilex 5" --part=A5ED065BB23AE6SR0
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207
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2025.08.29.13:55:53 Info: a5e_reset_release: "Transforming system: a5e_reset_release"
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208
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2025.08.29.13:55:53 Info: a5e_reset_release: "Naming system components in system: a5e_reset_release"
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209
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2025.08.29.13:55:53 Info: a5e_reset_release: "Processing generation queue"
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210
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2025.08.29.13:55:53 Info: a5e_reset_release: "Generating: a5e_reset_release"
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211
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2025.08.29.13:55:53 Info: a5e_reset_release: "Generating: intel_user_rst_clkgate"
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212
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2025.08.29.13:55:53 Info: a5e_reset_release: generating top-level entity intel_user_rst_clkgate
|
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213
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2025.08.29.13:55:53 Info: a5e_reset_release: Done "a5e_reset_release" with 2 modules, 3 files
|
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214
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2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis
|
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215
|
2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release.ip (a5e_reset_release) took 52 ms
|
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216
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2025.08.29.13:55:56 Info:
|
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217
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2025.08.29.13:55:56 Info: Generating on localhost:38361
|
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218
|
2025.08.29.13:55:56 Info: hps_subsys: All Generic Component instances match their respective ip files.
|
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219
|
2025.08.29.13:55:56 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/hps_subsys_generation.rpt
|
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220
|
2025.08.29.13:55:56 Info: Generated by version: 24.2 build 40
|
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221
|
2025.08.29.13:55:56 Info: Starting: Create HDL design files for synthesis
|
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222
|
2025.08.29.13:55:56 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys.qsys --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys --family="Agilex 5" --part=A5ED065BB23AE6SR0
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223
|
2025.08.29.13:55:56 Info: Loading mitysom-a5e-ref-base/hps_subsys.qsys
|
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224
|
2025.08.29.13:55:56 Info: Reading input file
|
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225
|
2025.08.29.13:55:56 Info: Parameterizing module hps_emif_0
|
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226
|
2025.08.29.13:55:56 Info: Parameterizing module intel_agilex_5_soc_0
|
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227
|
2025.08.29.13:55:56 Info: Parameterizing module lwhps2fpga_clock_bridge_0
|
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228
|
2025.08.29.13:55:56 Info: Parameterizing module lwhps2fpga_mm_bridge_0
|
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229
|
2025.08.29.13:55:56 Info: Parameterizing module lwhps2fpga_reset_bridge_0
|
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230
|
2025.08.29.13:55:56 Info: Building connections
|
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231
|
2025.08.29.13:55:56 Info: Parameterizing connections
|
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232
|
2025.08.29.13:55:56 Info: Validating
|
|
233
|
2025.08.29.13:55:56 Info: Done reading input file
|
|
234
|
2025.08.29.13:55:56 Warning: hps_subsys.hps_emif_0: Warnings found in IP parameterization.
|
|
235
|
2025.08.29.13:55:56 Warning: hps_subsys.intel_agilex_5_soc_0: Warnings found in IP parameterization.
|
|
236
|
2025.08.29.13:55:56 Info: hps_subsys: "Transforming system: hps_subsys"
|
|
237
|
2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_ch0_axi and slave hps_emif_0.s0_axi4 because the master has araddr signal 44 bit wide, but the slave is 40 bit wide.
|
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238
|
2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_ch0_axi and slave hps_emif_0.s0_axi4 because the master has awaddr signal 44 bit wide, but the slave is 40 bit wide.
|
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239
|
2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_csr_axi and slave hps_emif_0.s0_axil because the master has araddr signal 32 bit wide, but the slave is 27 bit wide.
|
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240
|
2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_csr_axi and slave hps_emif_0.s0_axil because the master has awaddr signal 32 bit wide, but the slave is 27 bit wide.
|
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241
|
2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.lwhps2fpga and slave lwhps2fpga_mm_bridge_0.s0 because the master is of type axi4 and the slave is of type avalon.
|
|
242
|
2025.08.29.13:55:56 Info: hps_subsys: "Naming system components in system: hps_subsys"
|
|
243
|
2025.08.29.13:55:56 Info: hps_subsys: "Processing generation queue"
|
|
244
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys"
|
|
245
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_emif_hps_ph2_0"
|
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246
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_intel_agilex_5_soc_0"
|
|
247
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_lwhps2fpga_clock_bridge_0"
|
|
248
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_lwhps2fpga_mm_bridge_0"
|
|
249
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_lwhps2fpga_reset_bridge_0"
|
|
250
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_mm_interconnect_1920_ue6ubpy"
|
|
251
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_mm_interconnect_1920_h4ukhcq"
|
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252
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_mm_interconnect_1920_ukl47vq"
|
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253
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: altera_reset_controller"
|
|
254
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_axi_translator_1960_ay2hzoq"
|
|
255
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_axi_translator_1960_a4dyuji"
|
|
256
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_slave_translator_191_xg7rzxi"
|
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257
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_axi_master_ni_1990_gr772qq"
|
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258
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_slave_agent_1930_jxauz3i"
|
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259
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi"
|
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260
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_router_1921_4h6rgyq"
|
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261
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_router_1921_yn3ubdy"
|
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262
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_burst_adapter_1940_7qihjtq"
|
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263
|
2025.08.29.13:55:56 Info: my_altera_avalon_st_pipeline_stage: "Generating: my_altera_avalon_st_pipeline_stage"
|
|
264
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_demultiplexer_1921_yunnbka"
|
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265
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_multiplexer_1922_aabsgmy"
|
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266
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_demultiplexer_1921_sz775ga"
|
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267
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_multiplexer_1922_twwxe5a"
|
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268
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_t2myejy"
|
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269
|
2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_avalon_st_pipeline_stage_1930_oiupeiq"
|
|
270
|
2025.08.29.13:55:56 Info: hps_subsys: Done "hps_subsys" with 25 modules, 34 files
|
|
271
|
2025.08.29.13:55:56 Info: Finished: Create HDL design files for synthesis
|
|
272
|
2025.08.29.13:55:56 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys.qsys (hps_subsys) took 3281 ms
|
|
273
|
2025.08.29.13:55:56 Info:
|
|
274
|
2025.08.29.13:55:56 Info: Generating on localhost:37129
|
|
275
|
2025.08.29.13:55:56 Warning: a5e: sysid_qsys_0 declares assignment embeddedsw.cmacro.timestamp set to 0 that does not match 1756490137 declared in file a5e_sysid_qsys_0.ip
|
|
276
|
2025.08.29.13:55:56 Warning: a5e: sysid_qsys_0 declares assignment embeddedsw.dts.params.timestamp set to 0 that does not match 1756490137 declared in file a5e_sysid_qsys_0.ip
|
|
277
|
2025.08.29.13:55:56 Info: a5e: Generic Component validation completed with warnings.
|
|
278
|
2025.08.29.13:55:56 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/a5e_generation.rpt
|
|
279
|
2025.08.29.13:55:56 Info: Generated by version: 24.2 build 40
|
|
280
|
2025.08.29.13:55:56 Info: Starting: Create HDL design files for synthesis
|
|
281
|
2025.08.29.13:55:56 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e --family="Agilex 5" --part=A5ED065BB23AE6SR0
|
|
282
|
2025.08.29.13:55:56 Info: Loading mitysom-a5e-ref-base/a5e.qsys
|
|
283
|
2025.08.29.13:55:56 Info: Reading input file
|
|
284
|
2025.08.29.13:55:56 Info: Parameterizing module fabric_reset_bridge_0
|
|
285
|
2025.08.29.13:55:56 Info: Parameterizing module gts_rst_seq_left
|
|
286
|
2025.08.29.13:55:56 Info: Parameterizing module hps_subsys
|
|
287
|
2025.08.29.13:55:56 Info: Parameterizing module pio_inputs_0
|
|
288
|
2025.08.29.13:55:56 Info: Parameterizing module pio_outputs_0
|
|
289
|
2025.08.29.13:55:56 Info: Parameterizing module reset_release
|
|
290
|
2025.08.29.13:55:56 Info: Parameterizing module sysid_qsys_0
|
|
291
|
2025.08.29.13:55:56 Info: Building connections
|
|
292
|
2025.08.29.13:55:56 Info: Parameterizing connections
|
|
293
|
2025.08.29.13:55:56 Info: Validating
|
|
294
|
2025.08.29.13:55:56 Info: Done reading input file
|
|
295
|
2025.08.29.13:55:56 Info: a5e: "Transforming system: a5e"
|
|
296
|
2025.08.29.13:55:56 Warning: hps_subsys.intel_agilex_5_soc_0_fpga2hps_interrupt: Cannot connect clock for irq_mapper.sender
|
|
297
|
2025.08.29.13:55:56 Warning: hps_subsys.intel_agilex_5_soc_0_fpga2hps_interrupt: Cannot connect reset for irq_mapper.sender
|
|
298
|
2025.08.29.13:55:56 Info: a5e: "Naming system components in system: a5e"
|
|
299
|
2025.08.29.13:55:56 Info: a5e: "Processing generation queue"
|
|
300
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e"
|
|
301
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_fabric_reset_bridge_0"
|
|
302
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_gts_rst_seq_left"
|
|
303
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_pio_inputs_0"
|
|
304
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_pio_outputs_0"
|
|
305
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_reset_release"
|
|
306
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_sysid_qsys_0"
|
|
307
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_mm_interconnect_1920_asemuny"
|
|
308
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_irq_mapper_2001_xwp5waq"
|
|
309
|
2025.08.29.13:55:56 Info: a5e: "Generating: altera_reset_controller"
|
|
310
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_master_translator_192_54w642y"
|
|
311
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_slave_translator_191_xg7rzxi"
|
|
312
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_master_agent_1930_l64uqry"
|
|
313
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_slave_agent_1930_jxauz3i"
|
|
314
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_avalon_sc_fifo_1932_22gxxgi"
|
|
315
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_router_1921_2xqdcwy"
|
|
316
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_router_1921_fckrxda"
|
|
317
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_traffic_limiter_1921_p3fvlba"
|
|
318
|
2025.08.29.13:55:56 Info: my_altera_avalon_sc_fifo_dest_id_fifo: "Generating: my_altera_avalon_sc_fifo_dest_id_fifo"
|
|
319
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_demultiplexer_1921_6rkx6dq"
|
|
320
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_multiplexer_1922_5rz7hqq"
|
|
321
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_demultiplexer_1921_wjv4adq"
|
|
322
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_multiplexer_1922_bpmqsti"
|
|
323
|
2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_a53nykq"
|
|
324
|
2025.08.29.13:55:56 Info: a5e: Done "a5e" with 24 modules, 24 files
|
|
325
|
2025.08.29.13:55:56 Info: Finished: Create HDL design files for synthesis
|
|
326
|
2025.08.29.13:55:56 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys (a5e) took 3033 ms
|
|
327
|
2025.08.29.13:55:56 Info:
|
|
328
|
2025.08.29.13:55:56 Info: Generating on localhost:44239
|
|
329
|
2025.08.29.13:55:56 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left/a5e_gts_rst_seq_left_generation.rpt
|
|
330
|
2025.08.29.13:55:56 Info: Generated by version: 24.2 build 40
|
|
331
|
2025.08.29.13:55:56 Info: Starting: Create HDL design files for synthesis
|
|
332
|
2025.08.29.13:55:56 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left --family="Agilex 5" --part=A5ED065BB23AE6SR0
|
|
333
|
2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Transforming system: a5e_gts_rst_seq_left"
|
|
334
|
2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Naming system components in system: a5e_gts_rst_seq_left"
|
|
335
|
2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Processing generation queue"
|
|
336
|
2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Generating: a5e_gts_rst_seq_left"
|
|
337
|
2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Generating: a5e_gts_rst_seq_left_intel_srcss_gts_310_n5l5zgq"
|
|
338
|
2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: Done "a5e_gts_rst_seq_left" with 2 modules, 6 files
|
|
339
|
2025.08.29.13:55:56 Info: Finished: Create HDL design files for synthesis
|
|
340
|
2025.08.29.13:55:56 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left.ip (a5e_gts_rst_seq_left) took 96 ms
|
|
341
|
2025.08.29.13:56:03 Info:
|
|
342
|
2025.08.29.13:56:03 Info: Generating on localhost:34205
|
|
343
|
2025.08.29.13:56:03 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/hps_subsys_intel_agilex_5_soc_0_generation.rpt
|
|
344
|
2025.08.29.13:56:03 Info: Generated by version: 24.2 build 40
|
|
345
|
2025.08.29.13:56:03 Info: Starting: Create HDL design files for synthesis
|
|
346
|
2025.08.29.13:56:03 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
|
|
347
|
2025.08.29.13:56:03 Warning: hps_subsys_intel_agilex_5_soc_0.intel_agilex_5_soc_0.sm_hps.hps_ccu_interconnect_rst: Associated reset sinks not declared
|
|
348
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0.intel_agilex_5_soc_0.sm_usb31_phy: For the device A5ED065BB23AE6SR0, CORE Speed Grade is {6} and HSSI Speed Grade is {0}
|
|
349
|
2025.08.29.13:56:03 Warning: hps_subsys_intel_agilex_5_soc_0.intel_agilex_5_soc_0.sm_usb31_phy: sm_usb31_phy.i_usb31_pipe_Rate must be exported, or connected to a matching conduit as it has unconnected inputs.
|
|
350
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Transforming system: hps_subsys_intel_agilex_5_soc_0"
|
|
351
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Naming system components in system: hps_subsys_intel_agilex_5_soc_0"
|
|
352
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Processing generation queue"
|
|
353
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0"
|
|
354
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq"
|
|
355
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza"
|
|
356
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy"
|
|
357
|
2025.08.29.13:56:03 Warning: sm_usb31_phy: Please note: VHDL is not supported in this release even if VHDL checkbox is opted.
|
|
358
|
2025.08.29.13:56:03 Info: sm_usb31_phy: Please note: VHDL is not supported in this release even if VHDL checkbox is opted.
|
|
359
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq"
|
|
360
|
2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: Done "hps_subsys_intel_agilex_5_soc_0" with 5 modules, 29 files
|
|
361
|
2025.08.29.13:56:03 Info: Finished: Create HDL design files for synthesis
|
|
362
|
2025.08.29.13:56:03 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip (hps_subsys_intel_agilex_5_soc_0) took 3861 ms
|
|
363
|
2025.08.29.13:58:43 Info:
|
|
364
|
2025.08.29.13:58:43 Info: Generating on localhost:41175
|
|
365
|
2025.08.29.13:58:43 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/hps_subsys_emif_hps_ph2_0_generation.rpt
|
|
366
|
2025.08.29.13:58:43 Info: Generated by version: 24.2 build 40
|
|
367
|
2025.08.29.13:58:43 Info: Starting: Create HDL design files for synthesis
|
|
368
|
2025.08.29.13:58:43 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
|
|
369
|
2025.08.29.13:58:43 Warning: hps_subsys_emif_hps_ph2_0.hps_emif_0: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases.
|
|
370
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6.
|
|
371
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0: Please place pins associated with the memory interfaces to bank 3A.
|
|
372
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0: Please only connect s0_axi4, s0_axil to Hard Processor System emif0_ch0, emif0_csr interface.
|
|
373
|
2025.08.29.13:58:43 Warning: hps_subsys_emif_hps_ph2_0.hps_emif_0.emif: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases.
|
|
374
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0.emif: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6.
|
|
375
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0.refclk_gpio: Intel GPIO supports a maximum interface frequency of 300 MHZ.
|
|
376
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Transforming system: hps_subsys_emif_hps_ph2_0"
|
|
377
|
2025.08.29.13:58:43 Warning: hps_emif_0: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases.
|
|
378
|
2025.08.29.13:58:43 Info: hps_emif_0: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6.
|
|
379
|
2025.08.29.13:58:43 Info: hps_emif_0: Please place pins associated with the memory interfaces to bank 3A.
|
|
380
|
2025.08.29.13:58:43 Info: hps_emif_0: Please only connect s0_axi4, s0_axil to Hard Processor System emif0_ch0, emif0_csr interface.
|
|
381
|
2025.08.29.13:58:43 Warning: hps_emif_0.emif: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases.
|
|
382
|
2025.08.29.13:58:43 Info: hps_emif_0.emif: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6.
|
|
383
|
2025.08.29.13:58:43 Info: hps_emif_0.refclk_gpio: Intel GPIO supports a maximum interface frequency of 300 MHZ.
|
|
384
|
2025.08.29.13:58:43 Warning: emif: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases.
|
|
385
|
2025.08.29.13:58:43 Info: emif: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6.
|
|
386
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Naming system components in system: hps_subsys_emif_hps_ph2_0"
|
|
387
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Processing generation queue"
|
|
388
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0"
|
|
389
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_hps_ph2_620_pqvxmzi"
|
|
390
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_620_l6fdbyq"
|
|
391
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_altera_gpio_2210_cdg66ya"
|
|
392
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_qsys_interface_bridge_10_irk3ocq"
|
|
393
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq"
|
|
394
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_cal_420_teac3ha"
|
|
395
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: altera_gpio"
|
|
396
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_cal_arch_fp_420_ewnru2a"
|
|
397
|
2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: Done "hps_subsys_emif_hps_ph2_0" with 9 modules, 58 files
|
|
398
|
2025.08.29.13:58:43 Info: Finished: Create HDL design files for synthesis
|
|
399
|
2025.08.29.13:58:43 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip (hps_subsys_emif_hps_ph2_0) took 97873 ms
|
|
400
|
2025.08.29.13:58:43 Info: Finished: Platform Designer system generation
|
|
401
|
quartus_stp a5e -c a5e
|
|
402
|
Info: *******************************************************************
|
|
403
|
Info: Running Quartus Prime Signal Tap
|
|
404
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
405
|
Info: Copyright (C) 2024 Intel Corporation. All rights reserved.
|
|
406
|
Info: Your use of Intel Corporation's design tools, logic functions
|
|
407
|
Info: and other software and tools, and any partner logic
|
|
408
|
Info: functions, and any output files from any of the foregoing
|
|
409
|
Info: (including device programming or simulation files), and any
|
|
410
|
Info: associated documentation or information are expressly subject
|
|
411
|
Info: to the terms and conditions of the Intel Program License
|
|
412
|
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
413
|
Info: the Intel FPGA IP License Agreement, or other applicable license
|
|
414
|
Info: agreement, including, without limitation, that your use is for
|
|
415
|
Info: the sole purpose of programming logic devices manufactured by
|
|
416
|
Info: Intel and sold by Intel or its authorized distributors. Please
|
|
417
|
Info: refer to the Intel FPGA Software License Subscription Agreements
|
|
418
|
Info: on the Quartus Prime software download page.
|
|
419
|
Info: Processing started: Fri Aug 29 13:58:44 2025
|
|
420
|
Info: System process ID: 1972104
|
|
421
|
Info: Command: quartus_stp a5e -c a5e
|
|
422
|
Info: Quartus Prime Signal Tap was successful. 0 errors, 0 warnings
|
|
423
|
Info: Peak virtual memory: 1017 megabytes
|
|
424
|
Info: Processing ended: Fri Aug 29 13:58:44 2025
|
|
425
|
Info: Elapsed time: 00:00:00
|
|
426
|
Info: System process ID: 1972104
|
|
427
|
quartus_sh --flow compile a5e.qpf -c a5e
|
|
428
|
Info: *******************************************************************
|
|
429
|
Info: Running Quartus Prime Shell
|
|
430
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
431
|
Info: Copyright (C) 2024 Intel Corporation. All rights reserved.
|
|
432
|
Info: Your use of Intel Corporation's design tools, logic functions
|
|
433
|
Info: and other software and tools, and any partner logic
|
|
434
|
Info: functions, and any output files from any of the foregoing
|
|
435
|
Info: (including device programming or simulation files), and any
|
|
436
|
Info: associated documentation or information are expressly subject
|
|
437
|
Info: to the terms and conditions of the Intel Program License
|
|
438
|
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
439
|
Info: the Intel FPGA IP License Agreement, or other applicable license
|
|
440
|
Info: agreement, including, without limitation, that your use is for
|
|
441
|
Info: the sole purpose of programming logic devices manufactured by
|
|
442
|
Info: Intel and sold by Intel or its authorized distributors. Please
|
|
443
|
Info: refer to the Intel FPGA Software License Subscription Agreements
|
|
444
|
Info: on the Quartus Prime software download page.
|
|
445
|
Info: Processing started: Fri Aug 29 13:58:45 2025
|
|
446
|
Info: System process ID: 1972122
|
|
447
|
Info: Command: quartus_sh --flow compile a5e.qpf -c a5e
|
|
448
|
Info: Quartus(args): compile a5e.qpf -c a5e
|
|
449
|
Info: Project Name = /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e
|
|
450
|
Info: Revision Name = a5e
|
|
451
|
Info: Run task: IP Generation
|
|
452
|
Info: *******************************************************************
|
|
453
|
Info: Running Quartus Prime IP Generation Tool
|
|
454
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
455
|
Info: Processing started: Fri Aug 29 13:58:45 2025
|
|
456
|
Info: System process ID: 1972141
|
|
457
|
Info: Command: quartus_ipgenerate a5e -c a5e --run_default_mode_op
|
|
458
|
Info: Found 13 IP file(s) in the project.
|
|
459
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys was found in the project.
|
|
460
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys.qsys was found in the project.
|
|
461
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip was found in the project.
|
|
462
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip was found in the project.
|
|
463
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip was found in the project.
|
|
464
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip was found in the project.
|
|
465
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip was found in the project.
|
|
466
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release.ip was found in the project.
|
|
467
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0.ip was found in the project.
|
|
468
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left.ip was found in the project.
|
|
469
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip was found in the project.
|
|
470
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0.ip was found in the project.
|
|
471
|
Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0.ip was found in the project.
|
|
472
|
Info: Finished generating IP file(s) in the project.
|
|
473
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/./a5e).
|
|
474
|
Info: Skipped generation of synthesis files for the Platform Designer IP file a5e.qsys based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
475
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/./hps_subsys).
|
|
476
|
Info: Skipped generation of synthesis files for the Platform Designer IP file hps_subsys.qsys based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
477
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0).
|
|
478
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
479
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0).
|
|
480
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
481
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0).
|
|
482
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
483
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0).
|
|
484
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
485
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0).
|
|
486
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
487
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release).
|
|
488
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_reset_release.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
489
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0).
|
|
490
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_fabric_reset_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
491
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left).
|
|
492
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_gts_rst_seq_left.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
493
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0).
|
|
494
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_sysid_qsys_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
495
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0).
|
|
496
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_pio_outputs_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
497
|
Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0).
|
|
498
|
Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_pio_inputs_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings).
|
|
499
|
Info: Quartus Prime IP Generation Tool was successful. 0 errors, 0 warnings
|
|
500
|
Info: Peak virtual memory: 1111 megabytes
|
|
501
|
Info: Processing ended: Fri Aug 29 13:58:46 2025
|
|
502
|
Info: Elapsed time: 00:00:01
|
|
503
|
Info: System process ID: 1972141
|
|
504
|
Info: Run task: HSSI Dual Simplex IP Generation
|
|
505
|
Info: *******************************************************************
|
|
506
|
Info: Running Quartus Prime Logic Generation Tool
|
|
507
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
508
|
Info: Processing started: Fri Aug 29 13:58:47 2025
|
|
509
|
Info: System process ID: 1972144
|
|
510
|
Info: Command: quartus_tlg --ds_tool --read_settings_files=on --write_settings_files=off --skip_quick_elaboration a5e -c a5e
|
|
511
|
Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_dr_tool_script.tcl
|
|
512
|
Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_ds_tool_script.tcl
|
|
513
|
Info: Launching DS tool
|
|
514
|
Info: qtlg_default_flow_script.tcl version: #1
|
|
515
|
Info: Initializing Hard-IP Logic Generation...
|
|
516
|
Info: Project = "a5e"
|
|
517
|
Info: Revision = "a5e"
|
|
518
|
Info: *******************************************************************
|
|
519
|
Info: Running Quartus Prime Logic Generation Tool
|
|
520
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
521
|
Info: Processing started: Fri Aug 29 13:58:47 2025
|
|
522
|
Info: System process ID: 1972147
|
|
523
|
Info: Command: quartus_tlg --read_settings_files=on --write_settings_files=off a5e -c a5e --dni --disable_qmsgdb --tool=ds_synth
|
|
524
|
Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_dr_tool_script.tcl
|
|
525
|
Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_ds_tool_script.tcl
|
|
526
|
Info: Launching tool main function ds_synthtool_main
|
|
527
|
Info: Quartus Prime Logic Generation Tool was successful. 0 errors, 0 warnings
|
|
528
|
Info: Peak virtual memory: 1119 megabytes
|
|
529
|
Info: Processing ended: Fri Aug 29 13:58:47 2025
|
|
530
|
Info: Elapsed time: 00:00:00
|
|
531
|
Info: System process ID: 1972147
|
|
532
|
Info: *******************************************************************
|
|
533
|
Info: Running Quartus Prime Logic Generation Tool
|
|
534
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
535
|
Info: Processing started: Fri Aug 29 13:58:48 2025
|
|
536
|
Info: System process ID: 1972149
|
|
537
|
Info: Command: quartus_tlg --read_settings_files=on --write_settings_files=off a5e -c a5e --dni --disable_qmsgdb --tool=ds_sim
|
|
538
|
Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_dr_tool_script.tcl
|
|
539
|
Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_ds_tool_script.tcl
|
|
540
|
Info: Launching tool main function ds_simtool_main
|
|
541
|
Info: Quartus Prime Logic Generation Tool was successful. 0 errors, 0 warnings
|
|
542
|
Info: Peak virtual memory: 1119 megabytes
|
|
543
|
Info: Processing ended: Fri Aug 29 13:58:49 2025
|
|
544
|
Info: Elapsed time: 00:00:01
|
|
545
|
Info: System process ID: 1972149
|
|
546
|
Info: Quartus Prime Logic Generation Tool was successful. 0 errors, 0 warnings
|
|
547
|
Info: Peak virtual memory: 1127 megabytes
|
|
548
|
Info: Processing ended: Fri Aug 29 13:58:49 2025
|
|
549
|
Info: Elapsed time: 00:00:02
|
|
550
|
Info: System process ID: 1972144
|
|
551
|
Info: Run task: Analysis & Synthesis
|
|
552
|
Info: *******************************************************************
|
|
553
|
Info: Running Quartus Prime Synthesis
|
|
554
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
555
|
Info: Processing started: Fri Aug 29 13:58:51 2025
|
|
556
|
Info: System process ID: 1972151
|
|
557
|
Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off a5e -c a5e
|
|
558
|
Info: qis_default_flow_script.tcl version: #1
|
|
559
|
Info: Initializing Synthesis...
|
|
560
|
Info: Project = "a5e"
|
|
561
|
Info: Revision = "a5e"
|
|
562
|
Info (21958): Initialized Quartus Message Database
|
|
563
|
Info: Analyzing source files
|
|
564
|
Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
|
|
565
|
Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file.
|
|
566
|
Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_reset_controller_1922/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
|
|
567
|
Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_reset_controller_1922/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_reset_controller_1922/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file.
|
|
568
|
Warning (16818): Verilog HDL warning at ff_macro_p2c.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/ff_macro_p2c.sv Line: 40
|
|
569
|
Warning (16818): Verilog HDL warning at ff_macro_c2p.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/ff_macro_c2p.sv Line: 40
|
|
570
|
Info (18437): Verilog HDL info at phy_staticmux.sv(324): previous definition of module tennm_sm_flux_dpma_clk_mux is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 324
|
|
571
|
Warning (16818): Verilog HDL warning at ff_macro_c2p.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_c2p.sv Line: 40
|
|
572
|
Warning (16818): Verilog HDL warning at ff_macro_p2c.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_p2c.sv Line: 40
|
|
573
|
Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv Line: 15
|
|
574
|
Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv Line: 15
|
|
575
|
Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv Line: 15
|
|
576
|
Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114
|
|
577
|
Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv Line: 15
|
|
578
|
Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv Line: 15
|
|
579
|
Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114
|
|
580
|
Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv Line: 15
|
|
581
|
Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 15
|
|
582
|
Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114
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583
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Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 15
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584
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Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv(16): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv Line: 16
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585
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Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114
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586
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Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv(16): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv Line: 16
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587
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Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv(16): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv Line: 16
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588
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Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114
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589
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Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv(16): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv Line: 16
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590
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Info: Elaborating from top-level entity "a5e_top"
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591
|
Info (18235): Library search order is as follows: "altera_merlin_master_translator_192; altera_merlin_slave_translator_191; altera_merlin_master_agent_1930; altera_merlin_slave_agent_1930; altera_avalon_sc_fifo_1932; altera_merlin_router_1921; altera_merlin_traffic_limiter_1921; altera_merlin_demultiplexer_1921; altera_merlin_multiplexer_1922; altera_mm_interconnect_1920; altera_irq_mapper_2001; altera_reset_controller_1922; a5e; intel_sundancemesa_hps_100; intel_usbphy_gts_100; intel_sundancemesa_mpfe_100; intel_agilex_5_soc_400; hps_subsys_intel_agilex_5_soc_0; emif_ph2_phy_arch_fp_620; emif_ph2_cal_arch_fp_420; emif_ph2_cal_420; emif_ph2_620; altera_gpio_core10_ph2_2210; altera_gpio_2210; qsys_interface_bridge_10; emif_hps_ph2_620; hps_subsys_emif_hps_ph2_0; hps_subsys_lwhps2fpga_clock_bridge_0; hps_subsys_lwhps2fpga_reset_bridge_0; altera_avalon_mm_bridge_2010; hps_subsys_lwhps2fpga_mm_bridge_0; altera_merlin_axi_translator_1960; altera_merlin_axi_master_ni_1990; altera_avalon_st_pipeline_stage_1930; altera_merlin_burst_adapter_1940; hps_subsys; intel_user_rst_clkgate_100; a5e_reset_release; a5e_fabric_reset_bridge_0; intel_srcss_gts_310; a5e_gts_rst_seq_left; altera_avalon_sysid_qsys_1916; a5e_sysid_qsys_0; altera_avalon_pio_1923; a5e_pio_outputs_0; a5e_pio_inputs_0". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER.
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592
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Warning (13471): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(786): value assigned to input "o_reconfig_readdata" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 786
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593
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Warning (13471): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(787): value assigned to input "o_reconfig_readdatavalid" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 787
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594
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Warning (13471): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(788): value assigned to input "o_reconfig_waitrequest" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 788
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595
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Info (19337): VHDL info at a5e_top.vhd(5): executing entity "a5e_top" with architecture "rtl" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 5
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596
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Warning (21570): VHDL warning at a5e_top.vhd(156): using initial value for 's_hps_gp_in' since it is never assigned File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 156
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597
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Warning (21570): VHDL warning at a5e_top.vhd(160): using initial value for 's_pio_inputs' since it is never assigned File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 160
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598
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Info (19337): VHDL info at altera_agilex_config_reset_release_endpoint.vhd(120): executing entity "altera_agilex_config_reset_release_endpoint" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd Line: 120
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599
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Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=0,receive_width=1,settings="{fabric agilex_config_reset_release dir agent psig 142e1a3c}")(1,60)" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126
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600
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Warning (16788): Net "core_fanoc_axi_intf[1].awprot[2]" does not have a driver at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(524) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 524
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601
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Warning (16788): Net "fbr_axi_adapter_intf[1].awid[6]" does not have a driver at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(526) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 526
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602
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Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(388): actual bit length 8 differs from formal bit length 7 for port "in_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 388
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603
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Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(389): actual bit length 8 differs from formal bit length 7 for port "out_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 389
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604
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Warning (13469): Verilog HDL assignment warning at hps_axi4_ready_latency_adapter.sv(394): truncated value with size 8 to match size of target (7) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 394
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605
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Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(426): actual bit length 41 differs from formal bit length 40 for port "in_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 426
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606
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Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(427): actual bit length 41 differs from formal bit length 40 for port "out_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 427
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607
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Warning (13469): Verilog HDL assignment warning at hps_axi4_ready_latency_adapter.sv(432): truncated value with size 41 to match size of target (40) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 432
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608
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Info (19337): VHDL info at altera_config_clock_source_endpoint.vhd(120): executing entity "altera_config_clock_source_endpoint" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_config_clock_source_endpoint.vhd Line: 120
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609
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Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=0,receive_width=1,settings="{fabric config_clock dir agent psig b4c631e1}")(1,45)" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126
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610
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Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(699): actual bit length 2 differs from formal bit length 18 for port "x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 699
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611
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Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(705): actual bit length 16 differs from formal bit length 40 for port "x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 705
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612
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Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(708): actual bit length 2 differs from formal bit length 4 for port "x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 708
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613
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Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(758): actual bit length 16 differs from formal bit length 40 for port "x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 758
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614
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Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(759): actual bit length 2 differs from formal bit length 4 for port "x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 759
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615
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Warning (13469): Verilog HDL assignment warning at hps_subsys_altera_merlin_axi_translator_1960_ay2hzoq.sv(718): truncated value with size 32 to match size of target (1) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_axi_translator_1960/synth/hps_subsys_altera_merlin_axi_translator_1960_ay2hzoq.sv Line: 718
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616
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Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(249): actual bit length 64 differs from formal bit length 1 for port "m0_buser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 249
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617
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Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(250): actual bit length 64 differs from formal bit length 1 for port "m0_ruser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 250
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618
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Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(287): actual bit length 64 differs from formal bit length 1 for port "s0_awuser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 287
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619
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Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(288): actual bit length 64 differs from formal bit length 1 for port "s0_aruser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 288
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620
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Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(289): actual bit length 64 differs from formal bit length 1 for port "s0_wuser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 289
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621
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Info (22567): Verilog HDL info at hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 127
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622
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Info (22567): Verilog HDL info at hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(126): extracting RAM for identifier 'mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 126
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623
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Info (22567): Verilog HDL info at hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 127
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624
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Info (22567): Verilog HDL info at a5e_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_avalon_sc_fifo_1932/synth/a5e_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 127
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625
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Info (13246): Can't recognize finite state machine "mgr_c_st" because it has a complex reset state
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626
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Info (13246): Can't recognize finite state machine "sub_c_st" because it has a complex reset state
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627
|
Info: Found 186 design entities
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628
|
Warning (21610): Output port "usb31_phy_reconfig_slave_readdatavalid" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0" of entity "hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_agilex_5_soc_400/synth/hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq.v Line: 113
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629
|
Warning (21610): Output port "usb31_phy_reconfig_slave_readdata[0..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0" of entity "hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_agilex_5_soc_400/synth/hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq.v Line: 116
|
|
630
|
Warning (21610): Output port "usb31_phy_reconfig_slave_waitrequest" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0" of entity "hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_agilex_5_soc_400/synth/hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq.v Line: 118
|
|
631
|
Warning (21610): Output port "hps2mpfe_ccu_rst[0]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.v Line: 127
|
|
632
|
Warning (21610): Output port "emif_mem_cfg_araddr[27..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 26
|
|
633
|
Warning (21610): Output port "emif_mem_cfg_awaddr[27..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 28
|
|
634
|
Warning (21610): Output port "emif_mem_cfg_arprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 35
|
|
635
|
Warning (21610): Output port "emif_mem_cfg_awprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 36
|
|
636
|
Warning (21610): Output port "emif0_araddr[40..43]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 51
|
|
637
|
Warning (21610): Output port "emif0_arlen[7]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 54
|
|
638
|
Warning (21610): Output port "emif0_arqos[2..3]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 56
|
|
639
|
Warning (21610): Output port "emif0_awaddr[40..43]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 60
|
|
640
|
Warning (21610): Output port "emif0_awlen[7]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 63
|
|
641
|
Warning (21610): Output port "emif0_awqos[2..3]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 65
|
|
642
|
Warning (21610): Output port "emif0_arprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 76
|
|
643
|
Warning (21610): Output port "emif0_awprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 77
|
|
644
|
Warning (21610): Output port "o_eth_rx_ch_clk" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_mux_sm_xcvrif_rx_ch_clk_mux_0" of entity "tennm_sm_xcvrif_rx_ch_clk_mux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 207
|
|
645
|
Warning (21610): Output port "o_eth_tx_ch_clk" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_mux_sm_xcvrif_tx_ch_clk_mux_0" of entity "tennm_sm_xcvrif_tx_ch_clk_mux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 248
|
|
646
|
Warning (21610): Output port "o_eth_rxword_clk" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_decoder_sm_flux_rx_rxword_clk_demux_0" of entity "tennm_sm_flux_rx_rxword_clk_demux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 58
|
|
647
|
Warning (21610): Output port "o_xcvrif[0..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_decoder_sm_flux_rx_demux_0" of entity "tennm_sm_flux_rx_demux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 22
|
|
648
|
Info: There are 239 partitions after elaboration.
|
|
649
|
Info: Running rule checking for Agilex5 protocol IPs...
|
|
650
|
Info (11170): Starting IP generation for the debug fabric: alt_sld_fab_0.
|
|
651
|
Info (11172): ***************************************************************
|
|
652
|
Info (11172): Quartus is a registered trademark of Intel Corporation in the
|
|
653
|
Info (11172): US and other countries. Portions of the Quartus Prime software
|
|
654
|
Info (11172): Code, and other portions of the code included in this download
|
|
655
|
Info (11172): Or on this DVD, are licensed to Intel Corporation and are the
|
|
656
|
Info (11172): Copyrighted property of third parties. For license details,
|
|
657
|
Info (11172): Refer to the End User License Agreement at
|
|
658
|
Info (11172): Http://fpgasoftware.intel.com/eula.
|
|
659
|
Info (11172): ***************************************************************
|
|
660
|
Info (11172): Deploying alt_sld_fab_0 to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0.ip
|
|
661
|
Info (11172): ***************************************************************
|
|
662
|
Info (11172): Quartus is a registered trademark of Intel Corporation in the
|
|
663
|
Info (11172): US and other countries. Portions of the Quartus Prime software
|
|
664
|
Info (11172): Code, and other portions of the code included in this download
|
|
665
|
Info (11172): Or on this DVD, are licensed to Intel Corporation and are the
|
|
666
|
Info (11172): Copyrighted property of third parties. For license details,
|
|
667
|
Info (11172): Refer to the End User License Agreement at
|
|
668
|
Info (11172): Http://fpgasoftware.intel.com/eula.
|
|
669
|
Info (11172): ***************************************************************
|
|
670
|
Info (11172): Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt
|
|
671
|
Info (11172): Generated by version: 24.2 build 40
|
|
672
|
Info (11172): Starting: Create HDL design files for synthesis
|
|
673
|
Info (11172): Qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0
|
|
674
|
Info (11172): Alt_sld_fab_0: "Transforming system: alt_sld_fab_0"
|
|
675
|
Info (11172): Alt_sld_fab_0: "Naming system components in system: alt_sld_fab_0"
|
|
676
|
Info (11172): Alt_sld_fab_0: "Processing generation queue"
|
|
677
|
Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0"
|
|
678
|
Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy"
|
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679
|
Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_1920_kp4kgry"
|
|
680
|
Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_sld_splitter_1920_3c4pkxy"
|
|
681
|
Info (11172): Alt_sld_fab_0: "Generating: altera_internal_oscillator_atom"
|
|
682
|
Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_cpztvzi"
|
|
683
|
Info (11172): Alt_sld_fab_0: Done "alt_sld_fab_0" with 6 modules, 8 files
|
|
684
|
Info (11172): Finished: Create HDL design files for synthesis
|
|
685
|
Info (11172): Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 347 ms
|
|
686
|
Info (11171): Finished IP generation for the debug fabric: alt_sld_fab_0.
|
|
687
|
Warning (23202): Intel FPGA IP Evaluation Mode feature is not used - it has been explicitly disabled for this design
|
|
688
|
Info: DA report generation in native DNI mode
|
|
689
|
Info (21615): Running Design Assistant Rules for snapshot 'partitioned'
|
|
690
|
Info: No waiver waived any violations
|
|
691
|
Info (22360): Design Assistant Results: 29 of 29 enabled rules passed, and 1 rules was disabled, in snapshot 'partitioned'
|
|
692
|
Info (21660): Design Assistant Results: 0 of 19 Critical severity rules issued violations in snapshot 'partitioned'
|
|
693
|
Info (21661): Design Assistant Results: 0 of 1 High severity rules issued violations in snapshot 'partitioned'
|
|
694
|
Info (21621): Design Assistant Results: 0 of 1 Medium severity rules issued violations in snapshot 'partitioned'
|
|
695
|
Info (21622): Design Assistant Results: 0 of 8 Low severity rules issued violations in snapshot 'partitioned'
|
|
696
|
Warning (23064): Input pin "ref_clk_0" of module instance "hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq:arch_0" is not connected. Its options will not be propagated. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_620_l6fdbyq.v Line: 128
|
|
697
|
Warning (23063): Option IO_STANDARD="1.1V TRUE DIFFERENTIAL SIGNALING" will be dropped.
|
|
698
|
Warning (23063): Option INPUT_TERMINATION="DIFFERENTIAL" will be dropped.
|
|
699
|
Warning (14284): Synthesized away the following node(s):
|
|
700
|
Warning (14285): Synthesized away the following node(s) of type RAM:
|
|
701
|
Warning (14320): Synthesized away node "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a32" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/tmp-clearbox/a5e/1972151/altera_syncram_impl_32r6.tdf Line: 934
|
|
702
|
Warning (14320): Synthesized away node "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a33" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/tmp-clearbox/a5e/1972151/altera_syncram_impl_32r6.tdf Line: 962
|
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703
|
Warning (14284): Synthesized away the following node(s):
|
|
704
|
Warning (14285): Synthesized away the following node(s) of type RAM:
|
|
705
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[0]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
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706
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[1]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
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707
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[2]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
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708
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[3]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
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709
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[4]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
710
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[5]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
711
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[6]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
712
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[7]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
713
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[0]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
714
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[1]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
715
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[2]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
716
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[3]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
717
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[4]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
718
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[5]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
719
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[6]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
720
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[7]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
721
|
Info: Synthesizing partition "root_partition"
|
|
722
|
Info (13014): Ignored 184 buffer(s)
|
|
723
|
Info (13019): Ignored 184 SOFT buffer(s)
|
|
724
|
Info (284007): State machine "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_13_1.sv Line: 394
|
|
725
|
Warning (14284): Synthesized away the following node(s):
|
|
726
|
Warning (14285): Synthesized away the following node(s) of type RAM:
|
|
727
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[45]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
728
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[45]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
729
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[46]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
730
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[46]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
731
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[47]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
732
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[47]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
733
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[48]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
734
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[48]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
735
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[49]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
736
|
Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[49]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95
|
|
737
|
Warning (13024): Output pins are stuck at VCC or GND
|
|
738
|
Warning (13410): Pin "o_usb31_mux_en" is stuck at VCC File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 40
|
|
739
|
Info (17049): 673 registers lost all their fanouts during netlist optimizations.
|
|
740
|
Info (21057): Implemented 2075 device resources after synthesis - the final resource count might be different
|
|
741
|
Info (21058): Implemented 19 input pins
|
|
742
|
Info (21059): Implemented 29 output pins
|
|
743
|
Info (21060): Implemented 68 bidirectional pins
|
|
744
|
Info (21061): Implemented 1765 logic cells
|
|
745
|
Info (21064): Implemented 151 RAM segments
|
|
746
|
Info (21071): Implemented 1 partitions
|
|
747
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a0" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
748
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a1" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
749
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a2" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
750
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a3" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
751
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a4" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
752
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a5" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
753
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a6" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
754
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a7" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
755
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a8" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
756
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a9" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
757
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a10" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
758
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a11" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
759
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a12" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
760
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a13" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
761
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a14" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
762
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a15" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
763
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a16" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
764
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a17" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
765
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a18" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
766
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a19" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
767
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a20" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
768
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a21" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
769
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a22" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
770
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a23" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
771
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a24" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
772
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a25" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
773
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a26" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
774
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a27" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
775
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a28" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
776
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a29" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
777
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a30" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
778
|
Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a31" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154
|
|
779
|
Info: Successfully synthesized partition
|
|
780
|
Info: Synthesizing partition "auto_fab_0"
|
|
781
|
Info (21057): Implemented 4 device resources after synthesis - the final resource count might be different
|
|
782
|
Info (21058): Implemented 0 input pins
|
|
783
|
Info (21059): Implemented 2 output pins
|
|
784
|
Info: Successfully synthesized partition
|
|
785
|
Info: Saving post-synthesis snapshots for 2 partition(s)
|
|
786
|
Info (21615): Running Design Assistant Rules for snapshot 'synthesized'
|
|
787
|
Info: No waiver waived any violations
|
|
788
|
Info (22360): Design Assistant Results: 14 of 14 enabled rules passed, and 7 rules was disabled, in snapshot 'synthesized'
|
|
789
|
Info (21661): Design Assistant Results: 0 of 2 High severity rules issued violations in snapshot 'synthesized'
|
|
790
|
Info (21621): Design Assistant Results: 0 of 6 Medium severity rules issued violations in snapshot 'synthesized'
|
|
791
|
Info (21622): Design Assistant Results: 0 of 6 Low severity rules issued violations in snapshot 'synthesized'
|
|
792
|
Info: Quartus Prime Synthesis was successful. 0 errors, 39 warnings
|
|
793
|
Info: Peak virtual memory: 2391 megabytes
|
|
794
|
Info: Processing ended: Fri Aug 29 13:59:44 2025
|
|
795
|
Info: Elapsed time: 00:00:53
|
|
796
|
Info: System process ID: 1972151
|
|
797
|
Info: Run task: Fitter
|
|
798
|
Info (20030): Parallel compilation is enabled and will use 24 of the 24 processors detected
|
|
799
|
Info: *******************************************************************
|
|
800
|
Info: Running Quartus Prime Fitter
|
|
801
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
802
|
Info: Processing started: Fri Aug 29 13:59:46 2025
|
|
803
|
Info: System process ID: 1972511
|
|
804
|
Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off a5e -c a5e
|
|
805
|
Info: qfit2_default_script.tcl version: #1
|
|
806
|
Info: Project = a5e
|
|
807
|
Info: Revision = a5e
|
|
808
|
Info (16677): Loading synthesized database.
|
|
809
|
Info (16734): Loading "synthesized" snapshot for partition "root_partition".
|
|
810
|
Info (16734): Loading "synthesized" snapshot for partition "auto_fab_0".
|
|
811
|
Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:03.
|
|
812
|
Info (119006): Selected device A5ED065BB23AE6SR0 for design "a5e"
|
|
813
|
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'.
|
|
814
|
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
|
|
815
|
Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
|
|
816
|
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'.
|
|
817
|
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
|
|
818
|
Info (12262): Starting Fitter periphery placement operations
|
|
819
|
Info (12290): Loading the periphery placement data.
|
|
820
|
Info (12291): Periphery placement data loaded: elapsed time is 00:00:25
|
|
821
|
Info (12627): Pin ~ALTERA_OSC_CLK_1~ is reserved at location BJ48
|
|
822
|
Info (12627): Pin ~ALTERA_AS_DATA1~ is reserved at location BV29
|
|
823
|
Info (12627): Pin ~ALTERA_AS_nCSO0,ALTERA_MSEL0~ is reserved at location BJ30
|
|
824
|
Info (12627): Pin ~ALTERA_AS_DATA2~ is reserved at location BR36
|
|
825
|
Info (12627): Pin ~ALTERA_AS_DATA0~ is reserved at location BN43
|
|
826
|
Info (12627): Pin ~ALTERA_AS_CLK~ is reserved at location BV26
|
|
827
|
Info (12627): Pin ~ALTERA_AS_nCSO2,ALTERA_MSEL1~ is reserved at location BN31
|
|
828
|
Info (12627): Pin ~ALTERA_AS_nCSO1,ALTERA_MSEL2~ is reserved at location BU29
|
|
829
|
Info (12627): Pin ~ALTERA_AS_DATA3~ is reserved at location BN38
|
|
830
|
Info (12627): Pin ~ALTERA_AS_nCSO3~ is reserved at location BJ39
|
|
831
|
Info (12627): Pin ~ALTERA_AS_nRST~ is reserved at location BJ41
|
|
832
|
Info (11685): 2 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins
|
|
833
|
Info (11684): Differential I/O pin "i_usb31_phy_refclk_p_clk" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "i_usb31_phy_refclk_p_clk(n)" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 42
|
|
834
|
Info (11684): Differential I/O pin "HPS_CLKIN_P" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "HPS_CLKIN_P(n)" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 18
|
|
835
|
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
|
|
836
|
Critical Warning (12677): No exact pin location assignment(s) for 32 pins of 116 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report
|
|
837
|
Info (16210): Plan updated with currently enabled project assignments.
|
|
838
|
Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00
|
|
839
|
Info (19755): Automatically applied size constraint on clock trees for periphery interfaces
|
|
840
|
Info (19756): Due to HSSI, height constrained fanout of clock u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|h2f_reset[0]
|
|
841
|
Info (19365): Global preservation of unused transceiver channels is enabled. All unused transceiver channels will be preserved.
|
|
842
|
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:00.
|
|
843
|
Info (332104): Reading SDC File: 'a5e.sdc'
|
|
844
|
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
|
|
845
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller'
|
|
846
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
847
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001'
|
|
848
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
849
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002'
|
|
850
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
851
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003'
|
|
852
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
853
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller'
|
|
854
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
855
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001'
|
|
856
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
857
|
Info (18794): Reading SDC File: 'ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc' for instance: 'u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps'
|
|
858
|
Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(12): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|s2f_user_clk1_hio could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 12
|
|
859
|
Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(18): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|f2s_gp* could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 18
|
|
860
|
Info (332104): Reading SDC File: 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq.sdc'
|
|
861
|
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
|
|
862
|
Warning (332174): Ignored filter at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl(187): u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0*div_reg could not be matched with a register File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl Line: 187
|
|
863
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller'
|
|
864
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
865
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001'
|
|
866
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
867
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002'
|
|
868
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
869
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003'
|
|
870
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
871
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller'
|
|
872
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
873
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001'
|
|
874
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
875
|
Info (332104): Reading SDC File: 'ip/a5e/a5e_reset_release/intel_user_rst_clkgate_100/synth/intel_user_rst_clkgate_agilex.sdc'
|
|
876
|
Info (18794): Reading SDC File: 'ip/a5e/a5e_gts_rst_seq_left/intel_srcss_gts_310/synth/a5e_gts_rst_seq_left_intel_srcss_gts_310_n5l5zgq.sdc' for instance: 'u0|gts_rst_seq_left|a5e_gts_rst_seq_left'
|
|
877
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
878
|
Info (332104): Reading SDC File: '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/qdb/_compiler/a5e/_flat/24.2.0/source/1/.temp/cpt_proxy/altera_internal_oscillator_atom.sdc'
|
|
879
|
Info (19449): Reading SDC files elapsed 00:00:00.
|
|
880
|
Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.
|
|
881
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[0].obuf from: i to: o
|
|
882
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[1].obuf from: i to: o
|
|
883
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[2].obuf from: i to: o
|
|
884
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[3].obuf from: i to: o
|
|
885
|
Warning (332158): Clock uncertainty characteristics of the Agilex 5 device family are preliminary
|
|
886
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
|
887
|
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
|
|
888
|
Info (332111): Found 32 clocks
|
|
889
|
Info (332111): Period Clock Name
|
|
890
|
Info (332111): ======== ============
|
|
891
|
Info (332111): 4.000 altera_int_osc_clk
|
|
892
|
Info (332111): 10.000 h2f_user0_clk_src
|
|
893
|
Info (332111): 40.000 HPS_CLK_25MHz
|
|
894
|
Info (332111): 7.500 HPS_CLKIN_P
|
|
895
|
Info (332111): 10.000 internal_clk
|
|
896
|
Info (332111): 2.500 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c0_cntr_0
|
|
897
|
Info (332111): 320.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c1_cntr_0
|
|
898
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[0]_in
|
|
899
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[0]_nff
|
|
900
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[1]_in
|
|
901
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[1]_nff
|
|
902
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[2]_in
|
|
903
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[2]_nff
|
|
904
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[3]_in
|
|
905
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[3]_nff
|
|
906
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_byte_rx_gated
|
|
907
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_rxclk_gated
|
|
908
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_byte_rx_gated
|
|
909
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_rxclk_gated
|
|
910
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_byte_rx_gated
|
|
911
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_rxclk_gated
|
|
912
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_byte_rx_gated
|
|
913
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_rxclk_gated
|
|
914
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_byte_rx_gated
|
|
915
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_rxclk_gated
|
|
916
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_byte_rx_gated
|
|
917
|
Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_rxclk_gated
|
|
918
|
Info (332111): 2.500 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_0
|
|
919
|
Info (332111): 320.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_sync_0
|
|
920
|
Info (332111): 7.500 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_pll_ncntr
|
|
921
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_base_0
|
|
922
|
Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_clk_periph_0
|
|
923
|
Info (176233): Starting register packing
|
|
924
|
Info (176235): Finished register packing
|
|
925
|
Extra Info (176218): Packed 32 registers into blocks of type Block RAM
|
|
926
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
927
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
928
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
929
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
930
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
931
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
932
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
933
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
934
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
935
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
936
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
937
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
938
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
939
|
Info (20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation.
|
|
940
|
Info (21624): Not running Design Assistant in plan stage because there is no enabled rule to check
|
|
941
|
Info (12517): Periphery placement operations ending: elapsed time is 00:01:20
|
|
942
|
Warning (15705): Ignored locations or region assignments to the following nodes
|
|
943
|
Warning (15706): Node "SFP_I2C_SCL" is assigned to location or region, but does not exist in design
|
|
944
|
Warning (15706): Node "SFP_I2C_SDA" is assigned to location or region, but does not exist in design
|
|
945
|
Warning (15706): Node "SFP_LOS" is assigned to location or region, but does not exist in design
|
|
946
|
Warning (15706): Node "SFP_MOD_PRSNT_N" is assigned to location or region, but does not exist in design
|
|
947
|
Warning (15706): Node "SFP_REFCLK_P" is assigned to location or region, but does not exist in design
|
|
948
|
Warning (15706): Node "SFP_RS0" is assigned to location or region, but does not exist in design
|
|
949
|
Warning (15706): Node "SFP_RX_N" is assigned to location or region, but does not exist in design
|
|
950
|
Warning (15706): Node "SFP_RX_P" is assigned to location or region, but does not exist in design
|
|
951
|
Warning (15706): Node "SFP_TX_DIS" is assigned to location or region, but does not exist in design
|
|
952
|
Warning (15706): Node "SFP_TX_FLT_N" is assigned to location or region, but does not exist in design
|
|
953
|
Warning (15706): Node "SFP_TX_N" is assigned to location or region, but does not exist in design
|
|
954
|
Warning (15706): Node "SFP_TX_P" is assigned to location or region, but does not exist in design
|
|
955
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
956
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
957
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
958
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
959
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
960
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
961
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
962
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
963
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
964
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
965
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
966
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
967
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
968
|
Info (11165): Fitter preparation operations ending: elapsed time is 00:01:11
|
|
969
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
970
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
971
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
972
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
973
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
974
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
975
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
976
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
977
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
978
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
979
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
980
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
981
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
982
|
Info (22300): Design uses Placement Effort Multiplier = 1.0.
|
|
983
|
Info (14951): The Fitter is using Advanced Physical Optimization.
|
|
984
|
Info (11888): Total time spent on timing analysis during Global Placement is 0.00 seconds.
|
|
985
|
Info (18252): The Fitter is using Physical Synthesis.
|
|
986
|
Info (18258): Fitter Physical Synthesis operations beginning
|
|
987
|
Info (18259): Fitter Physical Synthesis operations ending: elapsed time is 00:00:00
|
|
988
|
Info (11888): Total time spent on timing analysis during Physical Synthesis is 0.00 seconds.
|
|
989
|
Info (11178): Promoted 3 clocks
|
|
990
|
Info (18386): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|h2f_reset[0] (1 fanout) drives clock sector (0, 2)
|
|
991
|
Info (18386): auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|intosc|clk (1 fanout) drives clock sector (0, 2)
|
|
992
|
Info (18386): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|user0_clk[0] (1554 fanout) drives clock sector (0, 2)
|
|
993
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
994
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
995
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
996
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
997
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
998
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
999
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1000
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1001
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1002
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1003
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1004
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1005
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
1006
|
Info (22300): Design uses Placement Effort Multiplier = 1.0.
|
|
1007
|
Info (170189): Fitter placement preparation operations beginning
|
|
1008
|
Info (11888): Total time spent on timing analysis during Physical Synthesis is 0.00 seconds.
|
|
1009
|
Info (22300): Design uses Placement Effort Multiplier = 1.0.
|
|
1010
|
Info (170191): Fitter placement operations beginning
|
|
1011
|
Info (170137): Fitter placement was successful
|
|
1012
|
Info (170192): Fitter placement operations ending: elapsed time is 00:00:09
|
|
1013
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1014
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1015
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1016
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1017
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1018
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1019
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1020
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1021
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1022
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1023
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1024
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1025
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
1026
|
Info (11888): Total time spent on timing analysis during Placement is 0.01 seconds.
|
|
1027
|
Info (21624): Not running Design Assistant in place stage because there is no enabled rule to check
|
|
1028
|
Info (22300): Design uses Placement Effort Multiplier = 1.0.
|
|
1029
|
Info (170193): Fitter routing operations beginning
|
|
1030
|
Info (20215): Router estimated peak short interconnect demand : 21% of down directional wire in region X24_Y144 to X35_Y148
|
|
1031
|
Info (20265): Estimated peak short right directional wire demand : 0% in region X0_Y0 to X11_Y7
|
|
1032
|
Info (20265): Estimated peak short left directional wire demand : 0% in region X12_Y120 to X23_Y127
|
|
1033
|
Info (20265): Estimated peak short up directional wire demand : 10% in region X24_Y136 to X35_Y143
|
|
1034
|
Info (20265): Estimated peak short down directional wire demand : 21% in region X24_Y144 to X35_Y148
|
|
1035
|
Info (20215): Router estimated peak long high speed interconnect demand : 81% of down directional wire in region X36_Y144 to X47_Y148
|
|
1036
|
Info (20265): Estimated peak long high speed right directional wire demand : 13% in region X12_Y144 to X23_Y148
|
|
1037
|
Info (20265): Estimated peak long high speed left directional wire demand : 36% in region X24_Y136 to X35_Y143
|
|
1038
|
Info (20265): Estimated peak long high speed up directional wire demand : 66% in region X36_Y136 to X47_Y143
|
|
1039
|
Info (20265): Estimated peak long high speed down directional wire demand : 81% in region X36_Y144 to X47_Y148
|
|
1040
|
Info (20315): Note that the router may use short wires to implement long connections at higher delay
|
|
1041
|
Info (170239): Router is attempting to preserve 0.11 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements.
|
|
1042
|
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'.
|
|
1043
|
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
|
|
1044
|
Info (11888): Total time spent on timing analysis during Routing is 0.25 seconds.
|
|
1045
|
Warning (18291): Timing characteristics of device A5ED065BB23AE6SR0 are preliminary
|
|
1046
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1047
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1048
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1049
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1050
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1051
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1052
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1053
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1054
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1055
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1056
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1057
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1058
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
1059
|
Info (16607): Fitter routing operations ending: elapsed time is 00:00:32
|
|
1060
|
Info (17966): Starting Hyper-Retimer operations.
|
|
1061
|
Info (18914): The Hyper-Retimer was unable to optimize the design due to retiming restrictions. Run Fast Forward Timing Closure Recommendations to see step-by-step suggestions for design changes and show the estimated performance improvement from making these changes.
|
|
1062
|
Info (17968): Completed Hyper-Retimer operations.
|
|
1063
|
Info (18821): Fitter Hyper-Retimer operations ending: elapsed time is 00:00:01
|
|
1064
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1065
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1066
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1067
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1068
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1069
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1070
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1071
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1072
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1073
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1074
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1075
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1076
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
1077
|
Info (18258): Fitter Physical Synthesis operations beginning
|
|
1078
|
Info (18259): Fitter Physical Synthesis operations ending: elapsed time is 00:00:00
|
|
1079
|
Info (16557): Fitter post-fit operations ending: elapsed time is 00:00:18
|
|
1080
|
Info (20274): Successfully committed final database.
|
|
1081
|
Info (21624): Not running Design Assistant in finalize stage because there is no enabled rule to check
|
|
1082
|
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
|
|
1083
|
Info: Quartus Prime Fitter was successful. 0 errors, 21 warnings
|
|
1084
|
Info: Peak virtual memory: 11381 megabytes
|
|
1085
|
Info: Processing ended: Fri Aug 29 14:03:11 2025
|
|
1086
|
Info: Elapsed time: 00:03:25
|
|
1087
|
Info: System process ID: 1972511
|
|
1088
|
Info: Run task: Timing Analysis (Signoff)
|
|
1089
|
Info (20030): Parallel compilation is enabled and will use 24 of the 24 processors detected
|
|
1090
|
Info: *******************************************************************
|
|
1091
|
Info: Running Quartus Prime Timing Analyzer
|
|
1092
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
1093
|
Info: Processing started: Fri Aug 29 14:03:13 2025
|
|
1094
|
Info: System process ID: 1973746
|
|
1095
|
Info: Command: quartus_sta a5e -c a5e --mode=finalize
|
|
1096
|
Info: qsta_default_script.tcl version: #1
|
|
1097
|
Info (16677): Loading final database.
|
|
1098
|
Info (16734): Loading "final" snapshot for partition "root_partition".
|
|
1099
|
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
|
|
1100
|
Info (16678): Successfully loaded final database: elapsed time is 00:00:04.
|
|
1101
|
Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'.
|
|
1102
|
Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
|
|
1103
|
Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:00.
|
|
1104
|
Info (332104): Reading SDC File: 'a5e.sdc'
|
|
1105
|
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
|
|
1106
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller'
|
|
1107
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1108
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001'
|
|
1109
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1110
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002'
|
|
1111
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1112
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003'
|
|
1113
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1114
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller'
|
|
1115
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1116
|
Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001'
|
|
1117
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1118
|
Info (18794): Reading SDC File: 'ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc' for instance: 'u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps'
|
|
1119
|
Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(12): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|s2f_user_clk1_hio could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 12
|
|
1120
|
Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(18): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|f2s_gp* could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 18
|
|
1121
|
Info (332104): Reading SDC File: 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq.sdc'
|
|
1122
|
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
|
|
1123
|
Info: Initializing DDR database for CORE hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq
|
|
1124
|
Info: Finding port-to-pin mapping for CORE: hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq INSTANCE: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0
|
|
1125
|
Warning (332174): Ignored filter at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl(187): u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0*div_reg could not be matched with a register File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl Line: 187
|
|
1126
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller'
|
|
1127
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller|*
|
|
1128
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001'
|
|
1129
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|*
|
|
1130
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002'
|
|
1131
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|*
|
|
1132
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003'
|
|
1133
|
Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|*
|
|
1134
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller'
|
|
1135
|
Info: Following instance found in the design - u0|rst_controller|*
|
|
1136
|
Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001'
|
|
1137
|
Info: Following instance found in the design - u0|rst_controller_001|*
|
|
1138
|
Info (332104): Reading SDC File: 'ip/a5e/a5e_reset_release/intel_user_rst_clkgate_100/synth/intel_user_rst_clkgate_agilex.sdc'
|
|
1139
|
Info (18794): Reading SDC File: 'ip/a5e/a5e_gts_rst_seq_left/intel_srcss_gts_310/synth/a5e_gts_rst_seq_left_intel_srcss_gts_310_n5l5zgq.sdc' for instance: 'u0|gts_rst_seq_left|a5e_gts_rst_seq_left'
|
|
1140
|
Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left
|
|
1141
|
Info (332104): Reading SDC File: '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/qdb/_compiler/a5e/_flat/24.2.0/source/1/.temp/cpt_proxy/altera_internal_oscillator_atom.sdc'
|
|
1142
|
Info (19449): Reading SDC files elapsed 00:00:00.
|
|
1143
|
Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.
|
|
1144
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[0].obuf from: i to: o
|
|
1145
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[1].obuf from: i to: o
|
|
1146
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[2].obuf from: i to: o
|
|
1147
|
Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[3].obuf from: i to: o
|
|
1148
|
Warning (332158): Clock uncertainty characteristics of the Agilex 5 device family are preliminary
|
|
1149
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
|
1150
|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
|
|
1151
|
Info (332146): Worst-case setup slack is 4.786
|
|
1152
|
Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions
|
|
1153
|
Info (332119): ========= =================== ========= ========== =====================
|
|
1154
|
Info (332119): 4.786 0.000 0 h2f_user0_clk_src Slow fix6 0C Model
|
|
1155
|
Info (332146): Worst-case hold slack is 0.001
|
|
1156
|
Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions
|
|
1157
|
Info (332119): ========= =================== ========= ========== =====================
|
|
1158
|
Info (332119): 0.001 0.000 0 h2f_user0_clk_src Slow fix6 0C Model
|
|
1159
|
Info (332119): 0.403 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_0 Fast fix6 0C Model
|
|
1160
|
Info (332146): Worst-case recovery slack is 7.742
|
|
1161
|
Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions
|
|
1162
|
Info (332119): ========= =================== ========= ========== =====================
|
|
1163
|
Info (332119): 7.742 0.000 0 h2f_user0_clk_src Slow fix6 0C Model
|
|
1164
|
Info (332146): Worst-case removal slack is 0.202
|
|
1165
|
Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions
|
|
1166
|
Info (332119): ========= =================== ========= ========== =====================
|
|
1167
|
Info (332119): 0.202 0.000 0 h2f_user0_clk_src Fast fix6 0C Model
|
|
1168
|
Info (332140): No Setup paths to report
|
|
1169
|
Info (332140): No Recovery paths to report
|
|
1170
|
Info (332146): Worst-case minimum pulse width slack is 0.000
|
|
1171
|
Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions
|
|
1172
|
Info (332119): ========= =================== ========= ========== =====================
|
|
1173
|
Info (332119): 0.000 0.000 0 altera_int_osc_clk Slow fix6 100C Model
|
|
1174
|
Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[0]_nff Slow fix6 0C Model
|
|
1175
|
Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[1]_nff Slow fix6 0C Model
|
|
1176
|
Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[2]_nff Slow fix6 0C Model
|
|
1177
|
Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[3]_nff Slow fix6 0C Model
|
|
1178
|
Info (332119): 0.433 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_clk_periph_0 Slow fix6 100C Model
|
|
1179
|
Info (332119): 0.506 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_base_0 Slow fix6 0C Model
|
|
1180
|
Info (332119): 0.840 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_0 Slow fix6 0C Model
|
|
1181
|
Info (332119): 1.137 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c0_cntr_0 Slow fix6 0C Model
|
|
1182
|
Info (332119): 2.000 0.000 0 h2f_user0_clk_src Slow fix6 100C Model
|
|
1183
|
Info (332119): 2.399 0.000 0 internal_clk Slow fix6 0C Model
|
|
1184
|
Info (332119): 2.996 0.000 0 HPS_CLKIN_P Slow fix6 0C Model
|
|
1185
|
Info (332119): 3.664 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_pll_ncntr Slow fix6 0C Model
|
|
1186
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_byte_rx_gated Slow fix6 100C Model
|
|
1187
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_rxclk_gated Slow fix6 100C Model
|
|
1188
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_byte_rx_gated Slow fix6 100C Model
|
|
1189
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_rxclk_gated Slow fix6 100C Model
|
|
1190
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_byte_rx_gated Slow fix6 100C Model
|
|
1191
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_rxclk_gated Slow fix6 100C Model
|
|
1192
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_byte_rx_gated Slow fix6 100C Model
|
|
1193
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_rxclk_gated Slow fix6 100C Model
|
|
1194
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_byte_rx_gated Slow fix6 100C Model
|
|
1195
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_rxclk_gated Slow fix6 100C Model
|
|
1196
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_byte_rx_gated Slow fix6 100C Model
|
|
1197
|
Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_rxclk_gated Slow fix6 100C Model
|
|
1198
|
Info (332119): 20.000 0.000 0 HPS_CLK_25MHz Slow fix6 100C Model
|
|
1199
|
Info (332119): 159.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c1_cntr_0 Slow fix6 0C Model
|
|
1200
|
Info (332114): Report Metastability (Slow fix6 100C Model): Found 3 synchronizer chains.
|
|
1201
|
Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design.
|
|
1202
|
|
|
1203
|
Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain))
|
|
1204
|
|
|
1205
|
Info (332114): Number of Synchronizer Chains Found: 3
|
|
1206
|
Info (332114): Shortest Synchronizer Chain: 3 Registers
|
|
1207
|
Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%.
|
|
1208
|
Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0%
|
|
1209
|
Info (332114): Report Metastability (Slow fix6 0C Model): Found 3 synchronizer chains.
|
|
1210
|
Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design.
|
|
1211
|
|
|
1212
|
Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain))
|
|
1213
|
|
|
1214
|
Info (332114): Number of Synchronizer Chains Found: 3
|
|
1215
|
Info (332114): Shortest Synchronizer Chain: 3 Registers
|
|
1216
|
Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%.
|
|
1217
|
Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0%
|
|
1218
|
Info (332114): Report Metastability (Fast fix6 0C Model): Found 3 synchronizer chains.
|
|
1219
|
Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design.
|
|
1220
|
|
|
1221
|
Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain))
|
|
1222
|
|
|
1223
|
Info (332114): Number of Synchronizer Chains Found: 3
|
|
1224
|
Info (332114): Shortest Synchronizer Chain: 3 Registers
|
|
1225
|
Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%.
|
|
1226
|
Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0%
|
|
1227
|
Info (332114): Report Metastability (Fast fix6 100C Model): Found 3 synchronizer chains.
|
|
1228
|
Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design.
|
|
1229
|
|
|
1230
|
Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain))
|
|
1231
|
|
|
1232
|
Info (332114): Number of Synchronizer Chains Found: 3
|
|
1233
|
Info (332114): Shortest Synchronizer Chain: 3 Registers
|
|
1234
|
Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%.
|
|
1235
|
Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0%
|
|
1236
|
Info (332102): Design is not fully constrained for setup requirements
|
|
1237
|
Info (332102): Design is not fully constrained for hold requirements
|
|
1238
|
Info (21615): Running Design Assistant Rules for snapshot 'final'
|
|
1239
|
Info: No waiver waived any violations
|
|
1240
|
Info (22360): Design Assistant Results: 82 of 84 enabled rules passed, and 10 rules was disabled, in snapshot 'final'
|
|
1241
|
Info (21661): Design Assistant Results: 0 of 34 High severity rules issued violations in snapshot 'final'
|
|
1242
|
Info (21621): Design Assistant Results: 2 of 34 Medium severity rules issued violations in snapshot 'final'. Please refer to DRC report '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/output_files/a5e.tq.drc.signoff.rpt' for more information
|
|
1243
|
Info (21622): Design Assistant Results: 0 of 16 Low severity rules issued violations in snapshot 'final'
|
|
1244
|
Info (24095): Timing requirements were met
|
|
1245
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
|
|
1246
|
Info: Peak virtual memory: 2583 megabytes
|
|
1247
|
Info: Processing ended: Fri Aug 29 14:03:20 2025
|
|
1248
|
Info: Elapsed time: 00:00:07
|
|
1249
|
Info: System process ID: 1973746
|
|
1250
|
Info: Run task: Assembler (Generate programming files)
|
|
1251
|
Info: *******************************************************************
|
|
1252
|
Info: Running Quartus Prime Assembler
|
|
1253
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
1254
|
Info: Processing started: Fri Aug 29 14:03:21 2025
|
|
1255
|
Info: System process ID: 1973772
|
|
1256
|
Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off a5e -c a5e
|
|
1257
|
Info (16677): Loading final database.
|
|
1258
|
Info (16734): Loading "final" snapshot for partition "root_partition".
|
|
1259
|
Info (16734): Loading "final" snapshot for partition "auto_fab_0".
|
|
1260
|
Info (16678): Successfully loaded final database: elapsed time is 00:00:03.
|
|
1261
|
Info (20553): Using CVP Hash 208298575db468857a1351c04ae651c82273887e9970a4423c65133f22d966aa
|
|
1262
|
Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings
|
|
1263
|
Info: Peak virtual memory: 4376 megabytes
|
|
1264
|
Info: Processing ended: Fri Aug 29 14:03:37 2025
|
|
1265
|
Info: Elapsed time: 00:00:16
|
|
1266
|
Info: System process ID: 1973772
|
|
1267
|
Info (21793): Quartus Prime Full Compilation was successful. 0 errors, 113 warnings
|
|
1268
|
Info (23030): Evaluation of Tcl script /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qsh_flowengine.tcl was successful
|
|
1269
|
Info: Quartus Prime Shell was successful. 0 errors, 113 warnings
|
|
1270
|
Info: Peak virtual memory: 1175 megabytes
|
|
1271
|
Info: Processing ended: Fri Aug 29 14:03:39 2025
|
|
1272
|
Info: Elapsed time: 00:04:54
|
|
1273
|
Info: System process ID: 1972122
|
|
1274
|
quartus_sh -t /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/check_timing.tcl -project a5e
|
|
1275
|
Info: *******************************************************************
|
|
1276
|
Info: Running Quartus Prime Shell
|
|
1277
|
Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition
|
|
1278
|
Info: Copyright (C) 2024 Intel Corporation. All rights reserved.
|
|
1279
|
Info: Your use of Intel Corporation's design tools, logic functions
|
|
1280
|
Info: and other software and tools, and any partner logic
|
|
1281
|
Info: functions, and any output files from any of the foregoing
|
|
1282
|
Info: (including device programming or simulation files), and any
|
|
1283
|
Info: associated documentation or information are expressly subject
|
|
1284
|
Info: to the terms and conditions of the Intel Program License
|
|
1285
|
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
|
|
1286
|
Info: the Intel FPGA IP License Agreement, or other applicable license
|
|
1287
|
Info: agreement, including, without limitation, that your use is for
|
|
1288
|
Info: the sole purpose of programming logic devices manufactured by
|
|
1289
|
Info: Intel and sold by Intel or its authorized distributors. Please
|
|
1290
|
Info: refer to the Intel FPGA Software License Subscription Agreements
|
|
1291
|
Info: on the Quartus Prime software download page.
|
|
1292
|
Info: Processing started: Fri Aug 29 14:03:39 2025
|
|
1293
|
Info: System process ID: 1973798
|
|
1294
|
Info: Command: quartus_sh -t /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/check_timing.tcl -project a5e
|
|
1295
|
Info: Quartus(args): -project a5e
|
|
1296
|
Worst-case Setup: 4.786
|
|
1297
|
Worst-case Hold: 0.001
|
|
1298
|
Worst-case Recovery: 7.742
|
|
1299
|
Worst-case Removal: 0.202
|
|
1300
|
Worst-case Minimum Pulse Width: 0.000
|
|
1301
|
Design Passed Timing
|
|
1302
|
Info (23030): Evaluation of Tcl script /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/check_timing.tcl was successful
|
|
1303
|
Info: Quartus Prime Shell was successful. 0 errors, 0 warnings
|
|
1304
|
Info: Peak virtual memory: 1167 megabytes
|
|
1305
|
Info: Processing ended: Fri Aug 29 14:03:40 2025
|
|
1306
|
Info: Elapsed time: 00:00:01
|
|
1307
|
Info: System process ID: 1973798
|
|
1308
|
git clone https://git.criticallink.com/git/u-boot-socfpga.git -b socfpga_v2023.10 software/bootloader/u-boot-socfpga
|
|
1309
|
Cloning into 'software/bootloader/u-boot-socfpga'...
|
|
1310
|
remote: Enumerating objects: 187023, done.
|
|
1311
|
remote: Counting objects: 100% (187023/187023), done.
|
|
1312
|
remote: Compressing objects: 100% (36101/36101), done.
|
|
1313
|
remote: Total 960027 (delta 154439), reused 175913 (delta 149633)
|
|
1314
|
Receiving objects: 100% (960027/960027), 171.65 MiB | 48.06 MiB/s, done.
|
|
1315
|
Resolving deltas: 100% (799780/799780), done.
|
|
1316
|
git clone https://github.com/altera-opensource/arm-trusted-firmware -b QPDS24.1_REL_GSRD_PR software/bootloader/arm-trusted-firmware
|
|
1317
|
Cloning into 'software/bootloader/arm-trusted-firmware'...
|
|
1318
|
remote: Enumerating objects: 148523, done.
|
|
1319
|
remote: Counting objects: 100% (9100/9100), done.
|
|
1320
|
remote: Compressing objects: 100% (3747/3747), done.
|
|
1321
|
remote: Total 148523 (delta 5575), reused 7986 (delta 5069), pack-reused 139423 (from 2)
|
|
1322
|
Receiving objects: 100% (148523/148523), 47.37 MiB | 35.27 MiB/s, done.
|
|
1323
|
Resolving deltas: 100% (99894/99894), done.
|
|
1324
|
Note: switching to 'afecefc0f3cf570cea101fd3a07ad2c58499b485'.
|
|
1325
|
|
|
1326
|
You are in 'detached HEAD' state. You can look around, make experimental
|
|
1327
|
changes and commit them, and you can discard any commits you make in this
|
|
1328
|
state without impacting any branches by switching back to a branch.
|
|
1329
|
|
|
1330
|
If you want to create a new branch to retain commits you create, you may
|
|
1331
|
do so (now or later) by using -c with the switch command. Example:
|
|
1332
|
|
|
1333
|
git switch -c <new-branch-name>
|
|
1334
|
|
|
1335
|
Or undo this operation with:
|
|
1336
|
|
|
1337
|
git switch -
|
|
1338
|
|
|
1339
|
Turn off this advice by setting config variable advice.detachedHead to false
|
|
1340
|
|
|
1341
|
sed -i 's/PLAT_UART0_BASE/PLAT_UART1_BASE/g' software/bootloader/arm-trusted-firmware/plat/intel/soc/common/include/platform_def.h
|
|
1342
|
CROSS_COMPILE=aarch64-none-linux-gnu- make -j 4 -C software/bootloader/arm-trusted-firmware PLAT=agilex5 bl31
|
|
1343
|
make[1]: Entering directory '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/software/bootloader/arm-trusted-firmware'
|
|
1344
|
/bin/sh: 1: aarch64-none-linux-gnu-gcc: not found
|
|
1345
|
/bin/sh: 1: aarch64-none-linux-gnu-gcc: not found
|
|
1346
|
CC lib/libc/abort.c
|
|
1347
|
make[1]: aarch64-none-linux-gnu-gcc: No such file or directory
|
|
1348
|
make[1]: *** [Makefile:1496: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/software/bootloader/arm-trusted-firmware/build/agilex5/release/libc/abort.o] Error 127
|
|
1349
|
make[1]: *** Waiting for unfinished jobs....
|
|
1350
|
make[1]: Leaving directory '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/software/bootloader/arm-trusted-firmware'
|
|
1351
|
make: *** [Makefile:524: software/bootloader/arm-trusted-firmware/build/agilex5/release/bl31.bin] Error 2
|
|
1352
|
kanevsky@fpga-sm:~/mitysom-a5e-ref/mitysom-a5e-ref-base$
|
