kanevsky@fpga-sm:~$ git clone -b pro_24.2_stable git://support.criticallink.com/home/git/mitysom-a5e-ref.git Cloning into 'mitysom-a5e-ref'... remote: Enumerating objects: 258, done. remote: Counting objects: 100% (258/258), done. remote: Compressing objects: 100% (249/249), done. remote: Total 258 (delta 138), reused 0 (delta 0), pack-reused 0 Receiving objects: 100% (258/258), 553.21 KiB | 2.14 MiB/s, done. Resolving deltas: 100% (138/138), done. kanevsky@fpga-sm:~$ ls fpga MCD4 mitysom-a5e-ref quartus.log quartus.rec snap kanevsky@fpga-sm:~$ cd mitysom-a5e-ref/ .git/ mitysom-a5e-ref-base/ mitysom-a5e-ref-sdram/ mitysom-a5e-ref-sfp/ kanevsky@fpga-sm:~$ cd mitysom-a5e-ref/mitysom-a5e-ref-base/ kanevsky@fpga-sm:~/mitysom-a5e-ref/mitysom-a5e-ref-base$ make jic Design config: AGILEX5_MODEL = mitysom PROJECT_NAME = a5e FPGA_EMIF = 0 QSFP_EXAMPLE = 0 SFP_EXAMPLE = 0 SDRAM_EN = 0 USB_EN = 1 TEST_FIXTURE = 0 qsys-generate --quartus-project=a5e.qpf --clear-output-directory --rev=a5e a5e.qsys --upgrade-ip-cores *************************************************************** Quartus is a registered trademark of Intel Corporation in the US and other countries. Portions of the Quartus Prime software code, and other portions of the code included in this download or on this DVD, are licensed to Intel Corporation and are the copyrighted property of third parties. For license details, refer to the End User License Agreement at http://fpgasoftware.intel.com/eula. *************************************************************** 2025.08.29.13:55:31 Info: IP upgrade skipped for Platform Designer system /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys 2025.08.29.13:55:31 Info: Starting to upgrade the IP cores in the Platform Designer system 2025.08.29.13:55:31 Info: Finished upgrading the ip cores qsys-script --qpf=none --script=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/update_sysid.tcl --system-file=a5e.qsys *************************************************************** Quartus is a registered trademark of Intel Corporation in the US and other countries. Portions of the Quartus Prime software code, and other portions of the code included in this download or on this DVD, are licensed to Intel Corporation and are the copyrighted property of third parties. For license details, refer to the End User License Agreement at http://fpgasoftware.intel.com/eula. *************************************************************** 2025.08.29.13:55:31 Info: Doing: qsys-script --quartus-project=none --script=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/update_sysid.tcl --system-file=a5e.qsys 2025.08.29.13:55:37 Info: get_module_property FILE 2025.08.29.13:55:37 Info: get_instances 2025.08.29.13:55:37 Info: get_instance_property fabric_reset_bridge_0 CLASS_NAME 2025.08.29.13:55:37 Info: load_component fabric_reset_bridge_0 2025.08.29.13:55:37 Info: get_instantiation_property IP_FILE 2025.08.29.13:55:37 Info: get_component_property CLASS_NAME 2025.08.29.13:55:37 Info: get_instance_property gts_rst_seq_left CLASS_NAME 2025.08.29.13:55:37 Info: load_component gts_rst_seq_left 2025.08.29.13:55:39 Info: get_instantiation_property IP_FILE 2025.08.29.13:55:39 Info: get_component_property CLASS_NAME 2025.08.29.13:55:39 Info: get_instance_property hps_subsys CLASS_NAME 2025.08.29.13:55:39 Info: get_instance_property pio_inputs_0 CLASS_NAME 2025.08.29.13:55:39 Info: load_component pio_inputs_0 2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE 2025.08.29.13:55:40 Info: get_component_property CLASS_NAME 2025.08.29.13:55:40 Info: get_instance_property pio_outputs_0 CLASS_NAME 2025.08.29.13:55:40 Info: load_component pio_outputs_0 2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE 2025.08.29.13:55:40 Info: get_component_property CLASS_NAME 2025.08.29.13:55:40 Info: get_instance_property reset_release CLASS_NAME 2025.08.29.13:55:40 Info: load_component reset_release 2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE 2025.08.29.13:55:40 Info: get_component_property CLASS_NAME 2025.08.29.13:55:40 Info: get_instance_property sysid_qsys_0 CLASS_NAME 2025.08.29.13:55:40 Info: load_component sysid_qsys_0 2025.08.29.13:55:40 Info: get_instantiation_property IP_FILE 2025.08.29.13:55:40 Info: get_component_property CLASS_NAME 2025.08.29.13:55:40 Info: load_system /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip 2025.08.29.13:55:40 Info: set_module_property GENERATION_ID 1756490137 2025.08.29.13:55:40 Info: validate_system 2025.08.29.13:55:40 Info: save_system /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip qsys-generate --quartus-project=a5e.qpf --clear-output-directory --rev=a5e a5e.qsys --synthesis=VERILOG *************************************************************** Quartus is a registered trademark of Intel Corporation in the US and other countries. Portions of the Quartus Prime software code, and other portions of the code included in this download or on this DVD, are licensed to Intel Corporation and are the copyrighted property of third parties. For license details, refer to the End User License Agreement at http://fpgasoftware.intel.com/eula. *************************************************************** 2025.08.29.13:55:45 Info: Parallel IP Generation is enabled. 2025.08.29.13:55:45 Info: Platform Designer will attempt to use 6 processors for parallel IP generation based on available number of processors and the total number of IP to be generated. 2025.08.29.13:55:45 Info: 2025.08.29.13:55:45 Info: Starting: Platform Designer system generation 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:44239 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0/hps_subsys_lwhps2fpga_mm_bridge_0_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Transforming system: hps_subsys_lwhps2fpga_mm_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Naming system components in system: hps_subsys_lwhps2fpga_mm_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Processing generation queue" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Generating: hps_subsys_lwhps2fpga_mm_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: "Generating: hps_subsys_lwhps2fpga_mm_bridge_0_altera_avalon_mm_bridge_2010_tex5a4i" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_mm_bridge_0: Done "hps_subsys_lwhps2fpga_mm_bridge_0" with 2 modules, 4 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip (hps_subsys_lwhps2fpga_mm_bridge_0) took 506 ms 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:33047 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0/a5e_pio_inputs_0_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: a5e_pio_inputs_0.pio_inputs_0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation. 2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Transforming system: a5e_pio_inputs_0" 2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Naming system components in system: a5e_pio_inputs_0" 2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Processing generation queue" 2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Generating: a5e_pio_inputs_0" 2025.08.29.13:55:53 Info: a5e_pio_inputs_0: "Generating: a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q" 2025.08.29.13:55:53 Info: pio_inputs_0: Starting RTL generation for module 'a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q' 2025.08.29.13:55:53 Info: pio_inputs_0: Generation command is [exec /opt/intelFPGA_pro/24.2/quartus/linux64//perl/bin/perl -I /opt/intelFPGA_pro/24.2/quartus/linux64//perl/lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/europa -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q --dir=/tmp/alt0329_13947256075190898555.dir/0001_pio_inputs_0_gen/ --quartus_dir=/opt/intelFPGA_pro/24.2/quartus --verilog --config=/tmp/alt0329_13947256075190898555.dir/0001_pio_inputs_0_gen//a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q_component_configuration.pl --do_build_sim=0 ] 2025.08.29.13:55:53 Info: pio_inputs_0: Done RTL generation for module 'a5e_pio_inputs_0_altera_avalon_pio_1923_syhhu2q' 2025.08.29.13:55:53 Info: a5e_pio_inputs_0: Done "a5e_pio_inputs_0" with 2 modules, 2 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0.ip (a5e_pio_inputs_0) took 641 ms 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:41175 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0/a5e_pio_outputs_0_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Transforming system: a5e_pio_outputs_0" 2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Naming system components in system: a5e_pio_outputs_0" 2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Processing generation queue" 2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Generating: a5e_pio_outputs_0" 2025.08.29.13:55:53 Info: a5e_pio_outputs_0: "Generating: a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma" 2025.08.29.13:55:53 Info: pio_outputs_0: Starting RTL generation for module 'a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma' 2025.08.29.13:55:53 Info: pio_outputs_0: Generation command is [exec /opt/intelFPGA_pro/24.2/quartus/linux64//perl/bin/perl -I /opt/intelFPGA_pro/24.2/quartus/linux64//perl/lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/europa -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin/perl_lib -I /opt/intelFPGA_pro/24.2/quartus/sopc_builder/bin -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/common -I /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /opt/intelFPGA_pro/24.2/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma --dir=/tmp/alt0329_3243888775806564021.dir/0001_pio_outputs_0_gen/ --quartus_dir=/opt/intelFPGA_pro/24.2/quartus --verilog --config=/tmp/alt0329_3243888775806564021.dir/0001_pio_outputs_0_gen//a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma_component_configuration.pl --do_build_sim=0 ] 2025.08.29.13:55:53 Info: pio_outputs_0: Done RTL generation for module 'a5e_pio_outputs_0_altera_avalon_pio_1923_ysnj6ma' 2025.08.29.13:55:53 Info: a5e_pio_outputs_0: Done "a5e_pio_outputs_0" with 2 modules, 2 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0.ip (a5e_pio_outputs_0) took 530 ms 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:44239 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0/hps_subsys_lwhps2fpga_reset_bridge_0_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Transforming system: hps_subsys_lwhps2fpga_reset_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Naming system components in system: hps_subsys_lwhps2fpga_reset_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Processing generation queue" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: "Generating: hps_subsys_lwhps2fpga_reset_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_reset_bridge_0: Done "hps_subsys_lwhps2fpga_reset_bridge_0" with 1 modules, 1 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip (hps_subsys_lwhps2fpga_reset_bridge_0) took 62 ms 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:41175 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0/a5e_fabric_reset_bridge_0_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Transforming system: a5e_fabric_reset_bridge_0" 2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Naming system components in system: a5e_fabric_reset_bridge_0" 2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Processing generation queue" 2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: "Generating: a5e_fabric_reset_bridge_0" 2025.08.29.13:55:53 Info: a5e_fabric_reset_bridge_0: Done "a5e_fabric_reset_bridge_0" with 1 modules, 1 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0.ip (a5e_fabric_reset_bridge_0) took 50 ms 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:33047 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0/a5e_sysid_qsys_0_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0.sysid_qsys_0: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0.sysid_qsys_0: Time stamp will be automatically updated when this component is generated. 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Transforming system: a5e_sysid_qsys_0" 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Naming system components in system: a5e_sysid_qsys_0" 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Processing generation queue" 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Generating: a5e_sysid_qsys_0" 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: "Generating: altera_avalon_sysid_qsys" 2025.08.29.13:55:53 Info: a5e_sysid_qsys_0: Done "a5e_sysid_qsys_0" with 2 modules, 2 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip (a5e_sysid_qsys_0) took 77 ms 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:41175 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0/hps_subsys_lwhps2fpga_clock_bridge_0_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Transforming system: hps_subsys_lwhps2fpga_clock_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Naming system components in system: hps_subsys_lwhps2fpga_clock_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Processing generation queue" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: "Generating: hps_subsys_lwhps2fpga_clock_bridge_0" 2025.08.29.13:55:53 Info: hps_subsys_lwhps2fpga_clock_bridge_0: Done "hps_subsys_lwhps2fpga_clock_bridge_0" with 1 modules, 1 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip (hps_subsys_lwhps2fpga_clock_bridge_0) took 49 ms 2025.08.29.13:55:53 Info: 2025.08.29.13:55:53 Info: Generating on localhost:33047 2025.08.29.13:55:53 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release/a5e_reset_release_generation.rpt 2025.08.29.13:55:53 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:53 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:53 Info: a5e_reset_release: "Transforming system: a5e_reset_release" 2025.08.29.13:55:53 Info: a5e_reset_release: "Naming system components in system: a5e_reset_release" 2025.08.29.13:55:53 Info: a5e_reset_release: "Processing generation queue" 2025.08.29.13:55:53 Info: a5e_reset_release: "Generating: a5e_reset_release" 2025.08.29.13:55:53 Info: a5e_reset_release: "Generating: intel_user_rst_clkgate" 2025.08.29.13:55:53 Info: a5e_reset_release: generating top-level entity intel_user_rst_clkgate 2025.08.29.13:55:53 Info: a5e_reset_release: Done "a5e_reset_release" with 2 modules, 3 files 2025.08.29.13:55:53 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:53 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release.ip (a5e_reset_release) took 52 ms 2025.08.29.13:55:56 Info: 2025.08.29.13:55:56 Info: Generating on localhost:38361 2025.08.29.13:55:56 Info: hps_subsys: All Generic Component instances match their respective ip files. 2025.08.29.13:55:56 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/hps_subsys_generation.rpt 2025.08.29.13:55:56 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:56 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:56 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys.qsys --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:56 Info: Loading mitysom-a5e-ref-base/hps_subsys.qsys 2025.08.29.13:55:56 Info: Reading input file 2025.08.29.13:55:56 Info: Parameterizing module hps_emif_0 2025.08.29.13:55:56 Info: Parameterizing module intel_agilex_5_soc_0 2025.08.29.13:55:56 Info: Parameterizing module lwhps2fpga_clock_bridge_0 2025.08.29.13:55:56 Info: Parameterizing module lwhps2fpga_mm_bridge_0 2025.08.29.13:55:56 Info: Parameterizing module lwhps2fpga_reset_bridge_0 2025.08.29.13:55:56 Info: Building connections 2025.08.29.13:55:56 Info: Parameterizing connections 2025.08.29.13:55:56 Info: Validating 2025.08.29.13:55:56 Info: Done reading input file 2025.08.29.13:55:56 Warning: hps_subsys.hps_emif_0: Warnings found in IP parameterization. 2025.08.29.13:55:56 Warning: hps_subsys.intel_agilex_5_soc_0: Warnings found in IP parameterization. 2025.08.29.13:55:56 Info: hps_subsys: "Transforming system: hps_subsys" 2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_ch0_axi and slave hps_emif_0.s0_axi4 because the master has araddr signal 44 bit wide, but the slave is 40 bit wide. 2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_ch0_axi and slave hps_emif_0.s0_axi4 because the master has awaddr signal 44 bit wide, but the slave is 40 bit wide. 2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_csr_axi and slave hps_emif_0.s0_axil because the master has araddr signal 32 bit wide, but the slave is 27 bit wide. 2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.io96b0_csr_axi and slave hps_emif_0.s0_axil because the master has awaddr signal 32 bit wide, but the slave is 27 bit wide. 2025.08.29.13:55:56 Info: Interconnect is inserted between master intel_agilex_5_soc_0.lwhps2fpga and slave lwhps2fpga_mm_bridge_0.s0 because the master is of type axi4 and the slave is of type avalon. 2025.08.29.13:55:56 Info: hps_subsys: "Naming system components in system: hps_subsys" 2025.08.29.13:55:56 Info: hps_subsys: "Processing generation queue" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_emif_hps_ph2_0" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_intel_agilex_5_soc_0" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_lwhps2fpga_clock_bridge_0" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_lwhps2fpga_mm_bridge_0" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_lwhps2fpga_reset_bridge_0" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_mm_interconnect_1920_ue6ubpy" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_mm_interconnect_1920_h4ukhcq" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_mm_interconnect_1920_ukl47vq" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: altera_reset_controller" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_axi_translator_1960_ay2hzoq" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_axi_translator_1960_a4dyuji" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_slave_translator_191_xg7rzxi" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_axi_master_ni_1990_gr772qq" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_slave_agent_1930_jxauz3i" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_router_1921_4h6rgyq" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_router_1921_yn3ubdy" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_burst_adapter_1940_7qihjtq" 2025.08.29.13:55:56 Info: my_altera_avalon_st_pipeline_stage: "Generating: my_altera_avalon_st_pipeline_stage" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_demultiplexer_1921_yunnbka" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_multiplexer_1922_aabsgmy" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_demultiplexer_1921_sz775ga" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_multiplexer_1922_twwxe5a" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_t2myejy" 2025.08.29.13:55:56 Info: hps_subsys: "Generating: hps_subsys_altera_avalon_st_pipeline_stage_1930_oiupeiq" 2025.08.29.13:55:56 Info: hps_subsys: Done "hps_subsys" with 25 modules, 34 files 2025.08.29.13:55:56 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:56 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys.qsys (hps_subsys) took 3281 ms 2025.08.29.13:55:56 Info: 2025.08.29.13:55:56 Info: Generating on localhost:37129 2025.08.29.13:55:56 Warning: a5e: sysid_qsys_0 declares assignment embeddedsw.cmacro.timestamp set to 0 that does not match 1756490137 declared in file a5e_sysid_qsys_0.ip 2025.08.29.13:55:56 Warning: a5e: sysid_qsys_0 declares assignment embeddedsw.dts.params.timestamp set to 0 that does not match 1756490137 declared in file a5e_sysid_qsys_0.ip 2025.08.29.13:55:56 Info: a5e: Generic Component validation completed with warnings. 2025.08.29.13:55:56 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/a5e_generation.rpt 2025.08.29.13:55:56 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:56 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:56 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:56 Info: Loading mitysom-a5e-ref-base/a5e.qsys 2025.08.29.13:55:56 Info: Reading input file 2025.08.29.13:55:56 Info: Parameterizing module fabric_reset_bridge_0 2025.08.29.13:55:56 Info: Parameterizing module gts_rst_seq_left 2025.08.29.13:55:56 Info: Parameterizing module hps_subsys 2025.08.29.13:55:56 Info: Parameterizing module pio_inputs_0 2025.08.29.13:55:56 Info: Parameterizing module pio_outputs_0 2025.08.29.13:55:56 Info: Parameterizing module reset_release 2025.08.29.13:55:56 Info: Parameterizing module sysid_qsys_0 2025.08.29.13:55:56 Info: Building connections 2025.08.29.13:55:56 Info: Parameterizing connections 2025.08.29.13:55:56 Info: Validating 2025.08.29.13:55:56 Info: Done reading input file 2025.08.29.13:55:56 Info: a5e: "Transforming system: a5e" 2025.08.29.13:55:56 Warning: hps_subsys.intel_agilex_5_soc_0_fpga2hps_interrupt: Cannot connect clock for irq_mapper.sender 2025.08.29.13:55:56 Warning: hps_subsys.intel_agilex_5_soc_0_fpga2hps_interrupt: Cannot connect reset for irq_mapper.sender 2025.08.29.13:55:56 Info: a5e: "Naming system components in system: a5e" 2025.08.29.13:55:56 Info: a5e: "Processing generation queue" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_fabric_reset_bridge_0" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_gts_rst_seq_left" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_pio_inputs_0" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_pio_outputs_0" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_reset_release" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_sysid_qsys_0" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_mm_interconnect_1920_asemuny" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_irq_mapper_2001_xwp5waq" 2025.08.29.13:55:56 Info: a5e: "Generating: altera_reset_controller" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_master_translator_192_54w642y" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_slave_translator_191_xg7rzxi" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_master_agent_1930_l64uqry" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_slave_agent_1930_jxauz3i" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_avalon_sc_fifo_1932_22gxxgi" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_router_1921_2xqdcwy" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_router_1921_fckrxda" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_traffic_limiter_1921_p3fvlba" 2025.08.29.13:55:56 Info: my_altera_avalon_sc_fifo_dest_id_fifo: "Generating: my_altera_avalon_sc_fifo_dest_id_fifo" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_demultiplexer_1921_6rkx6dq" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_multiplexer_1922_5rz7hqq" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_demultiplexer_1921_wjv4adq" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_multiplexer_1922_bpmqsti" 2025.08.29.13:55:56 Info: a5e: "Generating: a5e_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_a53nykq" 2025.08.29.13:55:56 Info: a5e: Done "a5e" with 24 modules, 24 files 2025.08.29.13:55:56 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:56 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys (a5e) took 3033 ms 2025.08.29.13:55:56 Info: 2025.08.29.13:55:56 Info: Generating on localhost:44239 2025.08.29.13:55:56 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left/a5e_gts_rst_seq_left_generation.rpt 2025.08.29.13:55:56 Info: Generated by version: 24.2 build 40 2025.08.29.13:55:56 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:55:56 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Transforming system: a5e_gts_rst_seq_left" 2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Naming system components in system: a5e_gts_rst_seq_left" 2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Processing generation queue" 2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Generating: a5e_gts_rst_seq_left" 2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: "Generating: a5e_gts_rst_seq_left_intel_srcss_gts_310_n5l5zgq" 2025.08.29.13:55:56 Info: a5e_gts_rst_seq_left: Done "a5e_gts_rst_seq_left" with 2 modules, 6 files 2025.08.29.13:55:56 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:55:56 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left.ip (a5e_gts_rst_seq_left) took 96 ms 2025.08.29.13:56:03 Info: 2025.08.29.13:56:03 Info: Generating on localhost:34205 2025.08.29.13:56:03 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/hps_subsys_intel_agilex_5_soc_0_generation.rpt 2025.08.29.13:56:03 Info: Generated by version: 24.2 build 40 2025.08.29.13:56:03 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:56:03 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:56:03 Warning: hps_subsys_intel_agilex_5_soc_0.intel_agilex_5_soc_0.sm_hps.hps_ccu_interconnect_rst: Associated reset sinks not declared 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0.intel_agilex_5_soc_0.sm_usb31_phy: For the device A5ED065BB23AE6SR0, CORE Speed Grade is {6} and HSSI Speed Grade is {0} 2025.08.29.13:56:03 Warning: hps_subsys_intel_agilex_5_soc_0.intel_agilex_5_soc_0.sm_usb31_phy: sm_usb31_phy.i_usb31_pipe_Rate must be exported, or connected to a matching conduit as it has unconnected inputs. 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Transforming system: hps_subsys_intel_agilex_5_soc_0" 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Naming system components in system: hps_subsys_intel_agilex_5_soc_0" 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Processing generation queue" 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0" 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq" 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza" 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy" 2025.08.29.13:56:03 Warning: sm_usb31_phy: Please note: VHDL is not supported in this release even if VHDL checkbox is opted. 2025.08.29.13:56:03 Info: sm_usb31_phy: Please note: VHDL is not supported in this release even if VHDL checkbox is opted. 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: "Generating: hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" 2025.08.29.13:56:03 Info: hps_subsys_intel_agilex_5_soc_0: Done "hps_subsys_intel_agilex_5_soc_0" with 5 modules, 29 files 2025.08.29.13:56:03 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:56:03 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip (hps_subsys_intel_agilex_5_soc_0) took 3861 ms 2025.08.29.13:58:43 Info: 2025.08.29.13:58:43 Info: Generating on localhost:41175 2025.08.29.13:58:43 Info: Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/hps_subsys_emif_hps_ph2_0_generation.rpt 2025.08.29.13:58:43 Info: Generated by version: 24.2 build 40 2025.08.29.13:58:43 Info: Starting: Create HDL design files for synthesis 2025.08.29.13:58:43 Info: qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 2025.08.29.13:58:43 Warning: hps_subsys_emif_hps_ph2_0.hps_emif_0: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases. 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6. 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0: Please place pins associated with the memory interfaces to bank 3A. 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0: Please only connect s0_axi4, s0_axil to Hard Processor System emif0_ch0, emif0_csr interface. 2025.08.29.13:58:43 Warning: hps_subsys_emif_hps_ph2_0.hps_emif_0.emif: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases. 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0.emif: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6. 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0.hps_emif_0.refclk_gpio: Intel GPIO supports a maximum interface frequency of 300 MHZ. 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Transforming system: hps_subsys_emif_hps_ph2_0" 2025.08.29.13:58:43 Warning: hps_emif_0: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases. 2025.08.29.13:58:43 Info: hps_emif_0: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6. 2025.08.29.13:58:43 Info: hps_emif_0: Please place pins associated with the memory interfaces to bank 3A. 2025.08.29.13:58:43 Info: hps_emif_0: Please only connect s0_axi4, s0_axil to Hard Processor System emif0_ch0, emif0_csr interface. 2025.08.29.13:58:43 Warning: hps_emif_0.emif: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases. 2025.08.29.13:58:43 Info: hps_emif_0.emif: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6. 2025.08.29.13:58:43 Info: hps_emif_0.refclk_gpio: Intel GPIO supports a maximum interface frequency of 300 MHZ. 2025.08.29.13:58:43 Warning: emif: Timing is currently in a preliminary state. Designs will have to be recompiled in future releases. 2025.08.29.13:58:43 Info: emif: Configuring this IP for device A5ED065BB23AE6SR0 (Agilex 5). This device has speedgrade 6. 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Naming system components in system: hps_subsys_emif_hps_ph2_0" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Processing generation queue" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_hps_ph2_620_pqvxmzi" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_620_l6fdbyq" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_altera_gpio_2210_cdg66ya" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_qsys_interface_bridge_10_irk3ocq" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_cal_420_teac3ha" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: altera_gpio" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: "Generating: hps_subsys_emif_hps_ph2_0_emif_ph2_cal_arch_fp_420_ewnru2a" 2025.08.29.13:58:43 Info: hps_subsys_emif_hps_ph2_0: Done "hps_subsys_emif_hps_ph2_0" with 9 modules, 58 files 2025.08.29.13:58:43 Info: Finished: Create HDL design files for synthesis 2025.08.29.13:58:43 Info: Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip (hps_subsys_emif_hps_ph2_0) took 97873 ms 2025.08.29.13:58:43 Info: Finished: Platform Designer system generation quartus_stp a5e -c a5e Info: ******************************************************************* Info: Running Quartus Prime Signal Tap Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Copyright (C) 2024 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the Intel FPGA Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Fri Aug 29 13:58:44 2025 Info: System process ID: 1972104 Info: Command: quartus_stp a5e -c a5e Info: Quartus Prime Signal Tap was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1017 megabytes Info: Processing ended: Fri Aug 29 13:58:44 2025 Info: Elapsed time: 00:00:00 Info: System process ID: 1972104 quartus_sh --flow compile a5e.qpf -c a5e Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Copyright (C) 2024 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the Intel FPGA Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Fri Aug 29 13:58:45 2025 Info: System process ID: 1972122 Info: Command: quartus_sh --flow compile a5e.qpf -c a5e Info: Quartus(args): compile a5e.qpf -c a5e Info: Project Name = /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e Info: Revision Name = a5e Info: Run task: IP Generation Info: ******************************************************************* Info: Running Quartus Prime IP Generation Tool Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 13:58:45 2025 Info: System process ID: 1972141 Info: Command: quartus_ipgenerate a5e -c a5e --run_default_mode_op Info: Found 13 IP file(s) in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e.qsys was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys.qsys was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0.ip was found in the project. Info: IP file /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0.ip was found in the project. Info: Finished generating IP file(s) in the project. Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/./a5e). Info: Skipped generation of synthesis files for the Platform Designer IP file a5e.qsys based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/./hps_subsys). Info: Skipped generation of synthesis files for the Platform Designer IP file hps_subsys.qsys based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_emif_hps_ph2_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_lwhps2fpga_clock_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_lwhps2fpga_reset_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/hps_subsys/hps_subsys_lwhps2fpga_mm_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_reset_release). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_reset_release.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_fabric_reset_bridge_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_fabric_reset_bridge_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_gts_rst_seq_left). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_gts_rst_seq_left.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_sysid_qsys_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_sysid_qsys_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_outputs_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_pio_outputs_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Previously generated synthesis files were detected in the Platform Designer IP file generation directory (/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/a5e/a5e_pio_inputs_0). Info: Skipped generation of synthesis files for the Platform Designer IP file ip/a5e/a5e_pio_inputs_0.ip based on the current regeneration policy setting (Tools/Options/IP Settings). Info: Quartus Prime IP Generation Tool was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1111 megabytes Info: Processing ended: Fri Aug 29 13:58:46 2025 Info: Elapsed time: 00:00:01 Info: System process ID: 1972141 Info: Run task: HSSI Dual Simplex IP Generation Info: ******************************************************************* Info: Running Quartus Prime Logic Generation Tool Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 13:58:47 2025 Info: System process ID: 1972144 Info: Command: quartus_tlg --ds_tool --read_settings_files=on --write_settings_files=off --skip_quick_elaboration a5e -c a5e Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_dr_tool_script.tcl Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_ds_tool_script.tcl Info: Launching DS tool Info: qtlg_default_flow_script.tcl version: #1 Info: Initializing Hard-IP Logic Generation... Info: Project = "a5e" Info: Revision = "a5e" Info: ******************************************************************* Info: Running Quartus Prime Logic Generation Tool Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 13:58:47 2025 Info: System process ID: 1972147 Info: Command: quartus_tlg --read_settings_files=on --write_settings_files=off a5e -c a5e --dni --disable_qmsgdb --tool=ds_synth Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_dr_tool_script.tcl Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_ds_tool_script.tcl Info: Launching tool main function ds_synthtool_main Info: Quartus Prime Logic Generation Tool was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1119 megabytes Info: Processing ended: Fri Aug 29 13:58:47 2025 Info: Elapsed time: 00:00:00 Info: System process ID: 1972147 Info: ******************************************************************* Info: Running Quartus Prime Logic Generation Tool Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 13:58:48 2025 Info: System process ID: 1972149 Info: Command: quartus_tlg --read_settings_files=on --write_settings_files=off a5e -c a5e --dni --disable_qmsgdb --tool=ds_sim Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_dr_tool_script.tcl Info: Loading /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qtlg_ds_tool_script.tcl Info: Launching tool main function ds_simtool_main Info: Quartus Prime Logic Generation Tool was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1119 megabytes Info: Processing ended: Fri Aug 29 13:58:49 2025 Info: Elapsed time: 00:00:01 Info: System process ID: 1972149 Info: Quartus Prime Logic Generation Tool was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1127 megabytes Info: Processing ended: Fri Aug 29 13:58:49 2025 Info: Elapsed time: 00:00:02 Info: System process ID: 1972144 Info: Run task: Analysis & Synthesis Info: ******************************************************************* Info: Running Quartus Prime Synthesis Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 13:58:51 2025 Info: System process ID: 1972151 Info: Command: quartus_syn --read_settings_files=on --write_settings_files=off a5e -c a5e Info: qis_default_flow_script.tcl version: #1 Info: Initializing Synthesis... Info: Project = "a5e" Info: Revision = "a5e" Info (21958): Initialized Quartus Message Database Info: Analyzing source files Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file. Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv" (same filename, same library name and same md5 digest). Skipping analysis of this file. Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.v" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_reset_controller_1922/synth/altera_reset_controller.v" (same filename, same library name and same md5 digest). Skipping analysis of this file. Info (18237): File "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_reset_controller_1922/synth/altera_reset_synchronizer.v" is a duplicate of already analyzed file "/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_reset_controller_1922/synth/altera_reset_synchronizer.v" (same filename, same library name and same md5 digest). Skipping analysis of this file. Warning (16818): Verilog HDL warning at ff_macro_p2c.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/ff_macro_p2c.sv Line: 40 Warning (16818): Verilog HDL warning at ff_macro_c2p.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/ff_macro_c2p.sv Line: 40 Info (18437): Verilog HDL info at phy_staticmux.sv(324): previous definition of module tennm_sm_flux_dpma_clk_mux is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 324 Warning (16818): Verilog HDL warning at ff_macro_c2p.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_c2p.sv Line: 40 Warning (16818): Verilog HDL warning at ff_macro_p2c.sv(40): block identifier is required on this block File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/ready_latency/ff_macro_p2c.sv Line: 40 Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv Line: 15 Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_wide.sv Line: 15 Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv Line: 15 Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114 Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_hmc_slim.sv Line: 15 Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv Line: 15 Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114 Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_atom_inst_fa_noc.sv Line: 15 Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(15): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 15 Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114 Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(15): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 15 Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv(16): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv Line: 16 Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114 Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv(16): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_wide.sv Line: 16 Info (16884): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv(16): analyzing included file ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv Line: 16 Info (18437): Verilog HDL info at phy_arch_fp_interface.svh(114): previous definition of module AXI_BUS is here File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/phy_arch_fp_interface.svh Line: 114 Info (19624): Verilog HDL info at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv(16): back to file 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_fbr_axi_adapter_slim.sv Line: 16 Info: Elaborating from top-level entity "a5e_top" Info (18235): Library search order is as follows: "altera_merlin_master_translator_192; altera_merlin_slave_translator_191; altera_merlin_master_agent_1930; altera_merlin_slave_agent_1930; altera_avalon_sc_fifo_1932; altera_merlin_router_1921; altera_merlin_traffic_limiter_1921; altera_merlin_demultiplexer_1921; altera_merlin_multiplexer_1922; altera_mm_interconnect_1920; altera_irq_mapper_2001; altera_reset_controller_1922; a5e; intel_sundancemesa_hps_100; intel_usbphy_gts_100; intel_sundancemesa_mpfe_100; intel_agilex_5_soc_400; hps_subsys_intel_agilex_5_soc_0; emif_ph2_phy_arch_fp_620; emif_ph2_cal_arch_fp_420; emif_ph2_cal_420; emif_ph2_620; altera_gpio_core10_ph2_2210; altera_gpio_2210; qsys_interface_bridge_10; emif_hps_ph2_620; hps_subsys_emif_hps_ph2_0; hps_subsys_lwhps2fpga_clock_bridge_0; hps_subsys_lwhps2fpga_reset_bridge_0; altera_avalon_mm_bridge_2010; hps_subsys_lwhps2fpga_mm_bridge_0; altera_merlin_axi_translator_1960; altera_merlin_axi_master_ni_1990; altera_avalon_st_pipeline_stage_1930; altera_merlin_burst_adapter_1940; hps_subsys; intel_user_rst_clkgate_100; a5e_reset_release; a5e_fabric_reset_bridge_0; intel_srcss_gts_310; a5e_gts_rst_seq_left; altera_avalon_sysid_qsys_1916; a5e_sysid_qsys_0; altera_avalon_pio_1923; a5e_pio_outputs_0; a5e_pio_inputs_0". Quartus will look for undefined design units in your libraries in that order. To modify the ordering, please specify a semi-colon separated library list using the assignment LIBRARY_SEARCH_ORDER. Warning (13471): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(786): value assigned to input "o_reconfig_readdata" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 786 Warning (13471): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(787): value assigned to input "o_reconfig_readdatavalid" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 787 Warning (13471): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(788): value assigned to input "o_reconfig_waitrequest" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 788 Info (19337): VHDL info at a5e_top.vhd(5): executing entity "a5e_top" with architecture "rtl" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 5 Warning (21570): VHDL warning at a5e_top.vhd(156): using initial value for 's_hps_gp_in' since it is never assigned File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 156 Warning (21570): VHDL warning at a5e_top.vhd(160): using initial value for 's_pio_inputs' since it is never assigned File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 160 Info (19337): VHDL info at altera_agilex_config_reset_release_endpoint.vhd(120): executing entity "altera_agilex_config_reset_release_endpoint" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_agilex_config_reset_release_endpoint.vhd Line: 120 Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=0,receive_width=1,settings="{fabric agilex_config_reset_release dir agent psig 142e1a3c}")(1,60)" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126 Warning (16788): Net "core_fanoc_axi_intf[1].awprot[2]" does not have a driver at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(524) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 524 Warning (16788): Net "fbr_axi_adapter_intf[1].awid[6]" does not have a driver at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv(526) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_top.sv Line: 526 Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(388): actual bit length 8 differs from formal bit length 7 for port "in_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 388 Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(389): actual bit length 8 differs from formal bit length 7 for port "out_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 389 Warning (13469): Verilog HDL assignment warning at hps_axi4_ready_latency_adapter.sv(394): truncated value with size 8 to match size of target (7) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 394 Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(426): actual bit length 41 differs from formal bit length 40 for port "in_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 426 Warning (24541): Verilog HDL warning at hps_axi4_ready_latency_adapter.sv(427): actual bit length 41 differs from formal bit length 40 for port "out_data" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 427 Warning (13469): Verilog HDL assignment warning at hps_axi4_ready_latency_adapter.sv(432): truncated value with size 41 to match size of target (40) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/hps_axi4_ready_latency_adapter.sv Line: 432 Info (19337): VHDL info at altera_config_clock_source_endpoint.vhd(120): executing entity "altera_config_clock_source_endpoint" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_config_clock_source_endpoint.vhd Line: 120 Info (19337): VHDL info at altera_fabric_endpoint.vhd(126): executing entity "altera_fabric_endpoint(send_width=0,receive_width=1,settings="{fabric config_clock dir agent psig b4c631e1}")(1,45)" with architecture "rtl" File: /opt/intelFPGA_pro/24.2/quartus/libraries/megafunctions/altera_fabric_endpoint.vhd Line: 126 Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(699): actual bit length 2 differs from formal bit length 18 for port "x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdeemph" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 699 Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(705): actual bit length 16 differs from formal bit length 40 for port "x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdata" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 705 Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(708): actual bit length 2 differs from formal bit length 4 for port "x_std_sm_hssi_pcie_pcs_lane_0__i_txpipe_txdatak" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 708 Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(758): actual bit length 16 differs from formal bit length 40 for port "x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdata" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 758 Warning (24541): Verilog HDL warning at hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv(759): actual bit length 2 differs from formal bit length 4 for port "x_std_sm_hssi_pcie_pcs_lane_0__o_rxpipe_rxdatak" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_usbphy_gts_100_ctq4kfy.sv Line: 759 Warning (13469): Verilog HDL assignment warning at hps_subsys_altera_merlin_axi_translator_1960_ay2hzoq.sv(718): truncated value with size 32 to match size of target (1) File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_axi_translator_1960/synth/hps_subsys_altera_merlin_axi_translator_1960_ay2hzoq.sv Line: 718 Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(249): actual bit length 64 differs from formal bit length 1 for port "m0_buser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 249 Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(250): actual bit length 64 differs from formal bit length 1 for port "m0_ruser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 250 Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(287): actual bit length 64 differs from formal bit length 1 for port "s0_awuser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 287 Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(288): actual bit length 64 differs from formal bit length 1 for port "s0_aruser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 288 Warning (24541): Verilog HDL warning at hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v(289): actual bit length 64 differs from formal bit length 1 for port "s0_wuser" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_mm_interconnect_1920/synth/hps_subsys_altera_mm_interconnect_1920_h4ukhcq.v Line: 289 Info (22567): Verilog HDL info at hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 127 Info (22567): Verilog HDL info at hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(126): extracting RAM for identifier 'mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 126 Info (22567): Verilog HDL info at hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 127 Info (22567): Verilog HDL info at a5e_altera_avalon_sc_fifo_1932_22gxxgi.v(127): extracting RAM for identifier 'infer_mem' File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e/altera_avalon_sc_fifo_1932/synth/a5e_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 127 Info (13246): Can't recognize finite state machine "mgr_c_st" because it has a complex reset state Info (13246): Can't recognize finite state machine "sub_c_st" because it has a complex reset state Info: Found 186 design entities Warning (21610): Output port "usb31_phy_reconfig_slave_readdatavalid" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0" of entity "hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_agilex_5_soc_400/synth/hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq.v Line: 113 Warning (21610): Output port "usb31_phy_reconfig_slave_readdata[0..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0" of entity "hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_agilex_5_soc_400/synth/hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq.v Line: 116 Warning (21610): Output port "usb31_phy_reconfig_slave_waitrequest" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0" of entity "hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_agilex_5_soc_400/synth/hps_subsys_intel_agilex_5_soc_0_intel_agilex_5_soc_400_duzupmq.v Line: 118 Warning (21610): Output port "hps2mpfe_ccu_rst[0]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.v Line: 127 Warning (21610): Output port "emif_mem_cfg_araddr[27..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 26 Warning (21610): Output port "emif_mem_cfg_awaddr[27..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 28 Warning (21610): Output port "emif_mem_cfg_arprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 35 Warning (21610): Output port "emif_mem_cfg_awprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 36 Warning (21610): Output port "emif0_araddr[40..43]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 51 Warning (21610): Output port "emif0_arlen[7]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 54 Warning (21610): Output port "emif0_arqos[2..3]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 56 Warning (21610): Output port "emif0_awaddr[40..43]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 60 Warning (21610): Output port "emif0_awlen[7]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 63 Warning (21610): Output port "emif0_awqos[2..3]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 65 Warning (21610): Output port "emif0_arprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 76 Warning (21610): Output port "emif0_awprot[0..2]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_mpfe" of entity "hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_mpfe_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_mpfe_100_mqjw3gq.v Line: 77 Warning (21610): Output port "o_eth_rx_ch_clk" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_mux_sm_xcvrif_rx_ch_clk_mux_0" of entity "tennm_sm_xcvrif_rx_ch_clk_mux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 207 Warning (21610): Output port "o_eth_tx_ch_clk" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_mux_sm_xcvrif_tx_ch_clk_mux_0" of entity "tennm_sm_xcvrif_tx_ch_clk_mux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 248 Warning (21610): Output port "o_eth_rxword_clk" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_decoder_sm_flux_rx_rxword_clk_demux_0" of entity "tennm_sm_flux_rx_rxword_clk_demux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 58 Warning (21610): Output port "o_xcvrif[0..31]" in instance "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_usb31_phy|U_ch2_core|x_decoder_sm_flux_rx_demux_0" of entity "tennm_sm_flux_rx_demux" does not have a driver. Connecting to the default value "gnd". File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_usbphy_gts_100/synth/phy_staticmux.sv Line: 22 Info: There are 239 partitions after elaboration. Info: Running rule checking for Agilex5 protocol IPs... Info (11170): Starting IP generation for the debug fabric: alt_sld_fab_0. Info (11172): *************************************************************** Info (11172): Quartus is a registered trademark of Intel Corporation in the Info (11172): US and other countries. Portions of the Quartus Prime software Info (11172): Code, and other portions of the code included in this download Info (11172): Or on this DVD, are licensed to Intel Corporation and are the Info (11172): Copyrighted property of third parties. For license details, Info (11172): Refer to the End User License Agreement at Info (11172): Http://fpgasoftware.intel.com/eula. Info (11172): *************************************************************** Info (11172): Deploying alt_sld_fab_0 to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0.ip Info (11172): *************************************************************** Info (11172): Quartus is a registered trademark of Intel Corporation in the Info (11172): US and other countries. Portions of the Quartus Prime software Info (11172): Code, and other portions of the code included in this download Info (11172): Or on this DVD, are licensed to Intel Corporation and are the Info (11172): Copyrighted property of third parties. For license details, Info (11172): Refer to the End User License Agreement at Info (11172): Http://fpgasoftware.intel.com/eula. Info (11172): *************************************************************** Info (11172): Saving generation log to /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0/alt_sld_fab_0_generation.rpt Info (11172): Generated by version: 24.2 build 40 Info (11172): Starting: Create HDL design files for synthesis Info (11172): Qsys-generate /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0.ip --synthesis=VERILOG --output-directory=/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0 --family="Agilex 5" --part=A5ED065BB23AE6SR0 Info (11172): Alt_sld_fab_0: "Transforming system: alt_sld_fab_0" Info (11172): Alt_sld_fab_0: "Naming system components in system: alt_sld_fab_0" Info (11172): Alt_sld_fab_0: "Processing generation queue" Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0" Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_0_10_fkimwiy" Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_alt_sld_fab_1920_kp4kgry" Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_altera_sld_splitter_1920_3c4pkxy" Info (11172): Alt_sld_fab_0: "Generating: altera_internal_oscillator_atom" Info (11172): Alt_sld_fab_0: "Generating: alt_sld_fab_0_intel_agilex_reset_release_from_sdm_203_cpztvzi" Info (11172): Alt_sld_fab_0: Done "alt_sld_fab_0" with 6 modules, 8 files Info (11172): Finished: Create HDL design files for synthesis Info (11172): Generation of /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/dni/sandboxes/fpga-sm_1972151_0/sld/ipgen/alt_sld_fab_0.ip (alt_sld_fab_0) took 347 ms Info (11171): Finished IP generation for the debug fabric: alt_sld_fab_0. Warning (23202): Intel FPGA IP Evaluation Mode feature is not used - it has been explicitly disabled for this design Info: DA report generation in native DNI mode Info (21615): Running Design Assistant Rules for snapshot 'partitioned' Info: No waiver waived any violations Info (22360): Design Assistant Results: 29 of 29 enabled rules passed, and 1 rules was disabled, in snapshot 'partitioned' Info (21660): Design Assistant Results: 0 of 19 Critical severity rules issued violations in snapshot 'partitioned' Info (21661): Design Assistant Results: 0 of 1 High severity rules issued violations in snapshot 'partitioned' Info (21621): Design Assistant Results: 0 of 1 Medium severity rules issued violations in snapshot 'partitioned' Info (21622): Design Assistant Results: 0 of 8 Low severity rules issued violations in snapshot 'partitioned' Warning (23064): Input pin "ref_clk_0" of module instance "hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq:arch_0" is not connected. Its options will not be propagated. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_620_l6fdbyq.v Line: 128 Warning (23063): Option IO_STANDARD="1.1V TRUE DIFFERENTIAL SIGNALING" will be dropped. Warning (23063): Option INPUT_TERMINATION="DIFFERENTIAL" will be dropped. Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following node(s) of type RAM: Warning (14320): Synthesized away node "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a32" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/tmp-clearbox/a5e/1972151/altera_syncram_impl_32r6.tdf Line: 934 Warning (14320): Synthesized away node "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a33" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/tmp-clearbox/a5e/1972151/altera_syncram_impl_32r6.tdf Line: 962 Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following node(s) of type RAM: Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[0]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[1]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[2]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[3]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[4]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[5]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[6]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[7]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[0]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[1]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[2]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[3]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[4]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[5]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[6]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[7]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Info: Synthesizing partition "root_partition" Info (13014): Ignored 184 buffer(s) Info (13019): Ignored 184 SOFT buffer(s) Info (284007): State machine "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_burst_adapter|altera_merlin_burst_adapter_13_1.burst_adapter|state" will be implemented as a safe state machine. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_13_1.sv Line: 394 Warning (14284): Synthesized away the following node(s): Warning (14285): Synthesized away the following node(s) of type RAM: Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[45]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[45]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[46]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[46]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[47]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[47]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[48]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[48]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|ar_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[49]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (14320): Synthesized away node "u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|lwhps2fpga_axi4_rl_adp_inst|aw_inst_skid_buf|fifo_inst|a1|fifo_inst|mlab_inst|dout[49]" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/ready_latency/generic_mlab_sc.sv Line: 95 Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "o_usb31_mux_en" is stuck at VCC File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 40 Info (17049): 673 registers lost all their fanouts during netlist optimizations. Info (21057): Implemented 2075 device resources after synthesis - the final resource count might be different Info (21058): Implemented 19 input pins Info (21059): Implemented 29 output pins Info (21060): Implemented 68 bidirectional pins Info (21061): Implemented 1765 logic cells Info (21064): Implemented 151 RAM segments Info (21071): Implemented 1 partitions Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a0" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a1" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a2" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a3" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a4" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a5" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a6" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a7" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a8" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a9" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a10" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a11" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a12" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a13" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a14" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a15" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a16" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a17" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a18" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a19" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a20" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a21" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a22" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a23" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a24" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a25" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a26" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a27" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a28" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a29" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a30" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info (24545): In the "u0|hps_subsys|mm_interconnect_2|lwhps2fpga_mm_bridge_0_s0_agent_rdata_fifo|gen_blk9.gen_blk10_else.altera_syncram_component|auto_generated|altera_syncram_impl1|ram_block2a31" RAM Primitive, the optimization_option parameter with the auto value is no longer supported for the target device with the 6 speed grade. Hence, the parameter value has changed to high_speed. File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/hps_subsys/altera_avalon_sc_fifo_1932/synth/hps_subsys_altera_avalon_sc_fifo_1932_22gxxgi.v Line: 154 Info: Successfully synthesized partition Info: Synthesizing partition "auto_fab_0" Info (21057): Implemented 4 device resources after synthesis - the final resource count might be different Info (21058): Implemented 0 input pins Info (21059): Implemented 2 output pins Info: Successfully synthesized partition Info: Saving post-synthesis snapshots for 2 partition(s) Info (21615): Running Design Assistant Rules for snapshot 'synthesized' Info: No waiver waived any violations Info (22360): Design Assistant Results: 14 of 14 enabled rules passed, and 7 rules was disabled, in snapshot 'synthesized' Info (21661): Design Assistant Results: 0 of 2 High severity rules issued violations in snapshot 'synthesized' Info (21621): Design Assistant Results: 0 of 6 Medium severity rules issued violations in snapshot 'synthesized' Info (21622): Design Assistant Results: 0 of 6 Low severity rules issued violations in snapshot 'synthesized' Info: Quartus Prime Synthesis was successful. 0 errors, 39 warnings Info: Peak virtual memory: 2391 megabytes Info: Processing ended: Fri Aug 29 13:59:44 2025 Info: Elapsed time: 00:00:53 Info: System process ID: 1972151 Info: Run task: Fitter Info (20030): Parallel compilation is enabled and will use 24 of the 24 processors detected Info: ******************************************************************* Info: Running Quartus Prime Fitter Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 13:59:46 2025 Info: System process ID: 1972511 Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off a5e -c a5e Info: qfit2_default_script.tcl version: #1 Info: Project = a5e Info: Revision = a5e Info (16677): Loading synthesized database. Info (16734): Loading "synthesized" snapshot for partition "root_partition". Info (16734): Loading "synthesized" snapshot for partition "auto_fab_0". Info (16678): Successfully loaded synthesized database: elapsed time is 00:00:03. Info (119006): Selected device A5ED065BB23AE6SR0 for design "a5e" Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (171004): Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (12262): Starting Fitter periphery placement operations Info (12290): Loading the periphery placement data. Info (12291): Periphery placement data loaded: elapsed time is 00:00:25 Info (12627): Pin ~ALTERA_OSC_CLK_1~ is reserved at location BJ48 Info (12627): Pin ~ALTERA_AS_DATA1~ is reserved at location BV29 Info (12627): Pin ~ALTERA_AS_nCSO0,ALTERA_MSEL0~ is reserved at location BJ30 Info (12627): Pin ~ALTERA_AS_DATA2~ is reserved at location BR36 Info (12627): Pin ~ALTERA_AS_DATA0~ is reserved at location BN43 Info (12627): Pin ~ALTERA_AS_CLK~ is reserved at location BV26 Info (12627): Pin ~ALTERA_AS_nCSO2,ALTERA_MSEL1~ is reserved at location BN31 Info (12627): Pin ~ALTERA_AS_nCSO1,ALTERA_MSEL2~ is reserved at location BU29 Info (12627): Pin ~ALTERA_AS_DATA3~ is reserved at location BN38 Info (12627): Pin ~ALTERA_AS_nCSO3~ is reserved at location BJ39 Info (12627): Pin ~ALTERA_AS_nRST~ is reserved at location BJ41 Info (11685): 2 differential I/O pins do not have complementary pins. As a result, the Fitter automatically creates the complementary pins Info (11684): Differential I/O pin "i_usb31_phy_refclk_p_clk" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "i_usb31_phy_refclk_p_clk(n)" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 42 Info (11684): Differential I/O pin "HPS_CLKIN_P" does not have a complementary pin. As a result, the Fitter automatically creates the complementary pin "HPS_CLKIN_P(n)" File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/a5e_top.vhd Line: 18 Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details Critical Warning (12677): No exact pin location assignment(s) for 32 pins of 116 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report Info (16210): Plan updated with currently enabled project assignments. Info (12295): Periphery placement of all unplaced cells complete: elapsed time is 00:00:00 Info (19755): Automatically applied size constraint on clock trees for periphery interfaces Info (19756): Due to HSSI, height constrained fanout of clock u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|h2f_reset[0] Info (19365): Global preservation of unused transceiver channels is enabled. All unused transceiver channels will be preserved. Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:00. Info (332104): Reading SDC File: 'a5e.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller' Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001' Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002' Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003' Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller' Info: Following instance found in the design - u0|rst_controller|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001' Info: Following instance found in the design - u0|rst_controller_001|* Info (18794): Reading SDC File: 'ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc' for instance: 'u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps' Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(12): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|s2f_user_clk1_hio could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 12 Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(18): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|f2s_gp* could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 18 Info (332104): Reading SDC File: 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Warning (332174): Ignored filter at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl(187): u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0*div_reg could not be matched with a register File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl Line: 187 Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller' Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001' Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002' Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003' Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller' Info: Following instance found in the design - u0|rst_controller|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001' Info: Following instance found in the design - u0|rst_controller_001|* Info (332104): Reading SDC File: 'ip/a5e/a5e_reset_release/intel_user_rst_clkgate_100/synth/intel_user_rst_clkgate_agilex.sdc' Info (18794): Reading SDC File: 'ip/a5e/a5e_gts_rst_seq_left/intel_srcss_gts_310/synth/a5e_gts_rst_seq_left_intel_srcss_gts_310_n5l5zgq.sdc' for instance: 'u0|gts_rst_seq_left|a5e_gts_rst_seq_left' Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (332104): Reading SDC File: '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/qdb/_compiler/a5e/_flat/24.2.0/source/1/.temp/cpt_proxy/altera_internal_oscillator_atom.sdc' Info (19449): Reading SDC files elapsed 00:00:00. Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[0].obuf from: i to: o Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[1].obuf from: i to: o Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[2].obuf from: i to: o Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[3].obuf from: i to: o Warning (332158): Clock uncertainty characteristics of the Agilex 5 device family are preliminary Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 32 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 4.000 altera_int_osc_clk Info (332111): 10.000 h2f_user0_clk_src Info (332111): 40.000 HPS_CLK_25MHz Info (332111): 7.500 HPS_CLKIN_P Info (332111): 10.000 internal_clk Info (332111): 2.500 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c0_cntr_0 Info (332111): 320.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c1_cntr_0 Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[0]_in Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[0]_nff Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[1]_in Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[1]_nff Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[2]_in Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[2]_nff Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[3]_in Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[3]_nff Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_byte_rx_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_rxclk_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_byte_rx_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_rxclk_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_byte_rx_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_rxclk_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_byte_rx_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_rxclk_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_byte_rx_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_rxclk_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_byte_rx_gated Info (332111): 10.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_rxclk_gated Info (332111): 2.500 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_0 Info (332111): 320.000 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_sync_0 Info (332111): 7.500 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_pll_ncntr Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_base_0 Info (332111): 1.250 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_clk_periph_0 Info (176233): Starting register packing Info (176235): Finished register packing Extra Info (176218): Packed 32 registers into blocks of type Block RAM Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. Info (21624): Not running Design Assistant in plan stage because there is no enabled rule to check Info (12517): Periphery placement operations ending: elapsed time is 00:01:20 Warning (15705): Ignored locations or region assignments to the following nodes Warning (15706): Node "SFP_I2C_SCL" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_I2C_SDA" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_LOS" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_MOD_PRSNT_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_REFCLK_P" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_RS0" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_RX_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_RX_P" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_TX_DIS" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_TX_FLT_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_TX_N" is assigned to location or region, but does not exist in design Warning (15706): Node "SFP_TX_P" is assigned to location or region, but does not exist in design Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (11165): Fitter preparation operations ending: elapsed time is 00:01:11 Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (22300): Design uses Placement Effort Multiplier = 1.0. Info (14951): The Fitter is using Advanced Physical Optimization. Info (11888): Total time spent on timing analysis during Global Placement is 0.00 seconds. Info (18252): The Fitter is using Physical Synthesis. Info (18258): Fitter Physical Synthesis operations beginning Info (18259): Fitter Physical Synthesis operations ending: elapsed time is 00:00:00 Info (11888): Total time spent on timing analysis during Physical Synthesis is 0.00 seconds. Info (11178): Promoted 3 clocks Info (18386): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|h2f_reset[0] (1 fanout) drives clock sector (0, 2) Info (18386): auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|intosc|clk (1 fanout) drives clock sector (0, 2) Info (18386): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|user0_clk[0] (1554 fanout) drives clock sector (0, 2) Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (22300): Design uses Placement Effort Multiplier = 1.0. Info (170189): Fitter placement preparation operations beginning Info (11888): Total time spent on timing analysis during Physical Synthesis is 0.00 seconds. Info (22300): Design uses Placement Effort Multiplier = 1.0. Info (170191): Fitter placement operations beginning Info (170137): Fitter placement was successful Info (170192): Fitter placement operations ending: elapsed time is 00:00:09 Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (11888): Total time spent on timing analysis during Placement is 0.01 seconds. Info (21624): Not running Design Assistant in place stage because there is no enabled rule to check Info (22300): Design uses Placement Effort Multiplier = 1.0. Info (170193): Fitter routing operations beginning Info (20215): Router estimated peak short interconnect demand : 21% of down directional wire in region X24_Y144 to X35_Y148 Info (20265): Estimated peak short right directional wire demand : 0% in region X0_Y0 to X11_Y7 Info (20265): Estimated peak short left directional wire demand : 0% in region X12_Y120 to X23_Y127 Info (20265): Estimated peak short up directional wire demand : 10% in region X24_Y136 to X35_Y143 Info (20265): Estimated peak short down directional wire demand : 21% in region X24_Y144 to X35_Y148 Info (20215): Router estimated peak long high speed interconnect demand : 81% of down directional wire in region X36_Y144 to X47_Y148 Info (20265): Estimated peak long high speed right directional wire demand : 13% in region X12_Y144 to X23_Y148 Info (20265): Estimated peak long high speed left directional wire demand : 36% in region X24_Y136 to X35_Y143 Info (20265): Estimated peak long high speed up directional wire demand : 66% in region X36_Y136 to X47_Y143 Info (20265): Estimated peak long high speed down directional wire demand : 81% in region X36_Y144 to X47_Y148 Info (20315): Note that the router may use short wires to implement long connections at higher delay Info (170239): Router is attempting to preserve 0.11 percent of routes from an earlier compilation, a user specified Routing Constraints File, or internal routing requirements. Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (11888): Total time spent on timing analysis during Routing is 0.25 seconds. Warning (18291): Timing characteristics of device A5ED065BB23AE6SR0 are preliminary Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (16607): Fitter routing operations ending: elapsed time is 00:00:32 Info (17966): Starting Hyper-Retimer operations. Info (18914): The Hyper-Retimer was unable to optimize the design due to retiming restrictions. Run Fast Forward Timing Closure Recommendations to see step-by-step suggestions for design changes and show the estimated performance improvement from making these changes. Info (17968): Completed Hyper-Retimer operations. Info (18821): Fitter Hyper-Retimer operations ending: elapsed time is 00:00:01 Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info: Following instance found in the design - u0|rst_controller|* Info: Following instance found in the design - u0|rst_controller_001|* Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (18258): Fitter Physical Synthesis operations beginning Info (18259): Fitter Physical Synthesis operations ending: elapsed time is 00:00:00 Info (16557): Fitter post-fit operations ending: elapsed time is 00:00:18 Info (20274): Successfully committed final database. Info (21624): Not running Design Assistant in finalize stage because there is no enabled rule to check Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information. Info: Quartus Prime Fitter was successful. 0 errors, 21 warnings Info: Peak virtual memory: 11381 megabytes Info: Processing ended: Fri Aug 29 14:03:11 2025 Info: Elapsed time: 00:03:25 Info: System process ID: 1972511 Info: Run task: Timing Analysis (Signoff) Info (20030): Parallel compilation is enabled and will use 24 of the 24 processors detected Info: ******************************************************************* Info: Running Quartus Prime Timing Analyzer Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 14:03:13 2025 Info: System process ID: 1973746 Info: Command: quartus_sta a5e -c a5e --mode=finalize Info: qsta_default_script.tcl version: #1 Info (16677): Loading final database. Info (16734): Loading "final" snapshot for partition "root_partition". Info (16734): Loading "final" snapshot for partition "auto_fab_0". Info (16678): Successfully loaded final database: elapsed time is 00:00:04. Info (21076): High junction temperature operating condition is not set. Assuming a default value of '100'. Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'. Info (19539): Reading the HDL-embedded SDC files elapsed 00:00:00. Info (332104): Reading SDC File: 'a5e.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller' Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001' Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002' Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003' Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller' Info: Following instance found in the design - u0|rst_controller|* Info (18794): Reading SDC File: 'a5e/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001' Info: Following instance found in the design - u0|rst_controller_001|* Info (18794): Reading SDC File: 'ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc' for instance: 'u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps' Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(12): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|s2f_user_clk1_hio could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 12 Warning (332174): Ignored filter at hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc(18): u0|hps_subsys|intel_agilex_5_soc_0|intel_agilex_5_soc_0|sm_hps|sundancemesa_hps_inst|f2s_gp* could not be matched with a pin File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_intel_agilex_5_soc_0/intel_sundancemesa_hps_100/synth/hps_subsys_intel_agilex_5_soc_0_intel_sundancemesa_hps_100_mpsfcza.sdc Line: 18 Info (332104): Reading SDC File: 'ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Info: Initializing DDR database for CORE hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq Info: Finding port-to-pin mapping for CORE: hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq INSTANCE: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0 Warning (332174): Ignored filter at hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl(187): u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0*div_reg could not be matched with a register File: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/ip/hps_subsys/hps_subsys_emif_hps_ph2_0/emif_ph2_phy_arch_fp_620/synth/hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_timing_pins.tcl Line: 187 Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller' Info: Following instance found in the design - u0|hps_subsys|rst_controller|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_001' Info: Following instance found in the design - u0|hps_subsys|rst_controller_001|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_002' Info: Following instance found in the design - u0|hps_subsys|rst_controller_002|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|hps_subsys|rst_controller_003' Info: Following instance found in the design - u0|hps_subsys|rst_controller_003|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller' Info: Following instance found in the design - u0|rst_controller|* Info (18794): Reading SDC File: 'hps_subsys/altera_reset_controller_1922/synth/altera_reset_controller.sdc' for instance: 'u0|rst_controller_001' Info: Following instance found in the design - u0|rst_controller_001|* Info (332104): Reading SDC File: 'ip/a5e/a5e_reset_release/intel_user_rst_clkgate_100/synth/intel_user_rst_clkgate_agilex.sdc' Info (18794): Reading SDC File: 'ip/a5e/a5e_gts_rst_seq_left/intel_srcss_gts_310/synth/a5e_gts_rst_seq_left_intel_srcss_gts_310_n5l5zgq.sdc' for instance: 'u0|gts_rst_seq_left|a5e_gts_rst_seq_left' Info: IP SDC: u0|gts_rst_seq_left|a5e_gts_rst_seq_left Info (332104): Reading SDC File: '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/qdb/_compiler/a5e/_flat/24.2.0/source/1/.temp/cpt_proxy/altera_internal_oscillator_atom.sdc' Info (19449): Reading SDC files elapsed 00:00:00. Info (332097): The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network. Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[0].obuf from: i to: o Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[1].obuf from: i to: o Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[2].obuf from: i to: o Info (332098): Cell: u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0|hps_subsys_emif_hps_ph2_0_emif_ph2_phy_arch_fp_620_ybbqdzq_phy_arch_fp_inst|wrapper_bufs_mem|g_MEM_DQS_T_0_out[3].obuf from: i to: o Warning (332158): Clock uncertainty characteristics of the Agilex 5 device family are preliminary Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON Info (332146): Worst-case setup slack is 4.786 Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions Info (332119): ========= =================== ========= ========== ===================== Info (332119): 4.786 0.000 0 h2f_user0_clk_src Slow fix6 0C Model Info (332146): Worst-case hold slack is 0.001 Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions Info (332119): ========= =================== ========= ========== ===================== Info (332119): 0.001 0.000 0 h2f_user0_clk_src Slow fix6 0C Model Info (332119): 0.403 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_0 Fast fix6 0C Model Info (332146): Worst-case recovery slack is 7.742 Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions Info (332119): ========= =================== ========= ========== ===================== Info (332119): 7.742 0.000 0 h2f_user0_clk_src Slow fix6 0C Model Info (332146): Worst-case removal slack is 0.202 Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions Info (332119): ========= =================== ========= ========== ===================== Info (332119): 0.202 0.000 0 h2f_user0_clk_src Fast fix6 0C Model Info (332140): No Setup paths to report Info (332140): No Recovery paths to report Info (332146): Worst-case minimum pulse width slack is 0.000 Info (332119): Slack End Point TNS Failing End Points Clock Worst-Case Operating Conditions Info (332119): ========= =================== ========= ========== ===================== Info (332119): 0.000 0.000 0 altera_int_osc_clk Slow fix6 100C Model Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[0]_nff Slow fix6 0C Model Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[1]_nff Slow fix6 0C Model Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[2]_nff Slow fix6 0C Model Info (332119): 0.401 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_HPS_DQS_T[3]_nff Slow fix6 0C Model Info (332119): 0.433 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_clk_periph_0 Slow fix6 100C Model Info (332119): 0.506 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_vco_base_0 Slow fix6 0C Model Info (332119): 0.840 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_phy_clk_0 Slow fix6 0C Model Info (332119): 1.137 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c0_cntr_0 Slow fix6 0C Model Info (332119): 2.000 0.000 0 h2f_user0_clk_src Slow fix6 100C Model Info (332119): 2.399 0.000 0 internal_clk Slow fix6 0C Model Info (332119): 2.996 0.000 0 HPS_CLKIN_P Slow fix6 0C Model Info (332119): 3.664 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_pll_ncntr Slow fix6 0C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_byte_rx_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_0_rxclk_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_byte_rx_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_1_rxclk_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_byte_rx_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_2_rxclk_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_byte_rx_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_3_rxclk_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_byte_rx_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_4_rxclk_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_byte_rx_gated Slow fix6 100C Model Info (332119): 4.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_lane_5_rxclk_gated Slow fix6 100C Model Info (332119): 20.000 0.000 0 HPS_CLK_25MHz Slow fix6 100C Model Info (332119): 159.887 0.000 0 u0|hps_subsys|hps_emif_0|hps_emif_0|emif|arch_0_c1_cntr_0 Slow fix6 0C Model Info (332114): Report Metastability (Slow fix6 100C Model): Found 3 synchronizer chains. Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain)) Info (332114): Number of Synchronizer Chains Found: 3 Info (332114): Shortest Synchronizer Chain: 3 Registers Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0% Info (332114): Report Metastability (Slow fix6 0C Model): Found 3 synchronizer chains. Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain)) Info (332114): Number of Synchronizer Chains Found: 3 Info (332114): Shortest Synchronizer Chain: 3 Registers Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0% Info (332114): Report Metastability (Fast fix6 0C Model): Found 3 synchronizer chains. Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain)) Info (332114): Number of Synchronizer Chains Found: 3 Info (332114): Shortest Synchronizer Chain: 3 Registers Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0% Info (332114): Report Metastability (Fast fix6 100C Model): Found 3 synchronizer chains. Info (332114): The Design MTBF is not calculated because there are no specified synchronizers in the design. Info (332114): MTBF(design) = 1 / SUM(1 / MTBF(synchronizer chain)) Info (332114): Number of Synchronizer Chains Found: 3 Info (332114): Shortest Synchronizer Chain: 3 Registers Info (332114): Number of Chains For Which MTBFs Could Not be Calculated Due to Timing Violations: 0, or 0.0%. Info (332114): Number of Chains Excluded from MTBF Analysis: 3, or 100.0% Info (332102): Design is not fully constrained for setup requirements Info (332102): Design is not fully constrained for hold requirements Info (21615): Running Design Assistant Rules for snapshot 'final' Info: No waiver waived any violations Info (22360): Design Assistant Results: 82 of 84 enabled rules passed, and 10 rules was disabled, in snapshot 'final' Info (21661): Design Assistant Results: 0 of 34 High severity rules issued violations in snapshot 'final' Info (21621): Design Assistant Results: 2 of 34 Medium severity rules issued violations in snapshot 'final'. Please refer to DRC report '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/output_files/a5e.tq.drc.signoff.rpt' for more information Info (21622): Design Assistant Results: 0 of 16 Low severity rules issued violations in snapshot 'final' Info (24095): Timing requirements were met Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings Info: Peak virtual memory: 2583 megabytes Info: Processing ended: Fri Aug 29 14:03:20 2025 Info: Elapsed time: 00:00:07 Info: System process ID: 1973746 Info: Run task: Assembler (Generate programming files) Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Processing started: Fri Aug 29 14:03:21 2025 Info: System process ID: 1973772 Info: Command: quartus_asm --read_settings_files=on --write_settings_files=off a5e -c a5e Info (16677): Loading final database. Info (16734): Loading "final" snapshot for partition "root_partition". Info (16734): Loading "final" snapshot for partition "auto_fab_0". Info (16678): Successfully loaded final database: elapsed time is 00:00:03. Info (20553): Using CVP Hash 208298575db468857a1351c04ae651c82273887e9970a4423c65133f22d966aa Info: Quartus Prime Assembler was successful. 0 errors, 0 warnings Info: Peak virtual memory: 4376 megabytes Info: Processing ended: Fri Aug 29 14:03:37 2025 Info: Elapsed time: 00:00:16 Info: System process ID: 1973772 Info (21793): Quartus Prime Full Compilation was successful. 0 errors, 113 warnings Info (23030): Evaluation of Tcl script /opt/intelFPGA_pro/24.2/quartus/common/tcl/internal/qsh_flowengine.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 113 warnings Info: Peak virtual memory: 1175 megabytes Info: Processing ended: Fri Aug 29 14:03:39 2025 Info: Elapsed time: 00:04:54 Info: System process ID: 1972122 quartus_sh -t /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/check_timing.tcl -project a5e Info: ******************************************************************* Info: Running Quartus Prime Shell Info: Version 24.2.0 Build 40 06/27/2024 SC Pro Edition Info: Copyright (C) 2024 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the Intel FPGA Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Fri Aug 29 14:03:39 2025 Info: System process ID: 1973798 Info: Command: quartus_sh -t /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/check_timing.tcl -project a5e Info: Quartus(args): -project a5e Worst-case Setup: 4.786 Worst-case Hold: 0.001 Worst-case Recovery: 7.742 Worst-case Removal: 0.202 Worst-case Minimum Pulse Width: 0.000 Design Passed Timing Info (23030): Evaluation of Tcl script /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/scripts/check_timing.tcl was successful Info: Quartus Prime Shell was successful. 0 errors, 0 warnings Info: Peak virtual memory: 1167 megabytes Info: Processing ended: Fri Aug 29 14:03:40 2025 Info: Elapsed time: 00:00:01 Info: System process ID: 1973798 git clone https://git.criticallink.com/git/u-boot-socfpga.git -b socfpga_v2023.10 software/bootloader/u-boot-socfpga Cloning into 'software/bootloader/u-boot-socfpga'... remote: Enumerating objects: 187023, done. remote: Counting objects: 100% (187023/187023), done. remote: Compressing objects: 100% (36101/36101), done. remote: Total 960027 (delta 154439), reused 175913 (delta 149633) Receiving objects: 100% (960027/960027), 171.65 MiB | 48.06 MiB/s, done. Resolving deltas: 100% (799780/799780), done. git clone https://github.com/altera-opensource/arm-trusted-firmware -b QPDS24.1_REL_GSRD_PR software/bootloader/arm-trusted-firmware Cloning into 'software/bootloader/arm-trusted-firmware'... remote: Enumerating objects: 148523, done. remote: Counting objects: 100% (9100/9100), done. remote: Compressing objects: 100% (3747/3747), done. remote: Total 148523 (delta 5575), reused 7986 (delta 5069), pack-reused 139423 (from 2) Receiving objects: 100% (148523/148523), 47.37 MiB | 35.27 MiB/s, done. Resolving deltas: 100% (99894/99894), done. Note: switching to 'afecefc0f3cf570cea101fd3a07ad2c58499b485'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false sed -i 's/PLAT_UART0_BASE/PLAT_UART1_BASE/g' software/bootloader/arm-trusted-firmware/plat/intel/soc/common/include/platform_def.h CROSS_COMPILE=aarch64-none-linux-gnu- make -j 4 -C software/bootloader/arm-trusted-firmware PLAT=agilex5 bl31 make[1]: Entering directory '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/software/bootloader/arm-trusted-firmware' /bin/sh: 1: aarch64-none-linux-gnu-gcc: not found /bin/sh: 1: aarch64-none-linux-gnu-gcc: not found CC lib/libc/abort.c make[1]: aarch64-none-linux-gnu-gcc: No such file or directory make[1]: *** [Makefile:1496: /home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/software/bootloader/arm-trusted-firmware/build/agilex5/release/libc/abort.o] Error 127 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/home/kanevsky/mitysom-a5e-ref/mitysom-a5e-ref-base/software/bootloader/arm-trusted-firmware' make: *** [Makefile:524: software/bootloader/arm-trusted-firmware/build/agilex5/release/bl31.bin] Error 2 kanevsky@fpga-sm:~/mitysom-a5e-ref/mitysom-a5e-ref-base$