Activity
From 01/30/2026 to 02/28/2026
02/11/2026
- DR 01:15 AM Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hello Mike,
Thanks for the quick response and confirmation of the updated
documentation. We are working on implementation now and we will let you
know if we have any problems.
By the way, Ben Rodenbeck (copied on this email) i... - MF 12:33 AM Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Dean,
Sorry for the confusion! I see that was incorrect in the previous version of the datasheet now that I've checked the change log.
Let us know if you have any other questions!
- Mike
02/10/2026
- DR 11:55 PM Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Oh, I have an old version of the datasheet (August 8 2024) that says this. Grabbing the updated version now from your site. I think that clears up the issue, thanks!
- MF 11:09 PM Firmware: RE: Clock EN signal and I2C Dual purpose pin
- Hi Dean,
Pin AH2 is our CLKUSR enable pin. This does not leave the SOM and only goes to the enable pin of the 100 MHz oscillator. The output of the oscillator is then fed into Pin Y15. If you did not want to use the 100 MHz oscillator... - Regarding FPGA ball location AH2 "SCL_1V8". From my understanding, this pin can be driven low to enable the 100MHz CLKUSR on Y15. This is my global ref clock input.
This pin is labeled as "SCL_1V8" (I/O signal used for I2C).
Is it...