Activity
From 07/11/2024 to 08/09/2024
08/09/2024
(Posted on behalf of a customer)
On my existing system, the Max10 FPGA has the USB Blaster interface that uses 2.5V JTAG levels that I also route to a CPLD on my board. From the MitySOM-C10G documentation, the 10G uses 1.8V JTAG L...