Activity
From 05/11/2025 to 06/09/2025
05/30/2025
- RD 06:40 AM Software Development: RE: Enquiry about mcu_safety_error pin
- Hi Mike,
Thank you for your response.
We are working with the SDL (Safety Diagnostic Library), and as part of this, we have enabled DCC, ECC, and MCRC as per our requirements. Now, we are moving on to BIST (PBIST/LBIST).
As we u...
05/29/2025
- MW 09:23 AM Software Development: RE: Enquiry about mcu_safety_error pin
- Hello,
The MCU_ERRORn signal is not connected to the PMIC. It is pulled low on the board via a 4.7K resistor.
You do not need to include the LTC2945HUD-1#PBF in your design, but should remove it's entry in the device tree you boo... - Hello there,
Question 1. For the MitySOM AM62A, is the pin MCU_SAFETY_ERRORn connected to the PMIC ?
Question 2. Can you explain the logic of SOM Power Monitor circuit (U1 / LTC2945HUD-1#PBF) in your carrier board ? We have implem...
05/20/2025
- RD 05:29 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Jonathan,
Thank you for your support. It's clear now, and I see that they have provided the DDR ECC driver code in R5. I will look into it and try to inject and test DDR at runtime.
Thank you,
Rajkumar
05/19/2025
- JC 03:29 PM Software Development: RE: Enable DDR ECC in Am62A processor
- Rajkumar Dumala wrote in message#6956:
> Hi Jonathan,
> ...
05/16/2025
- RD 06:33 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Jonathan,
Thank you for the response.
I applied the three patches you provided to my current workspace, rebuilt U-Boot and the device tree, and it is working fine—the system is booting successfully.
However, I have a few doub...
05/14/2025
- JC 08:34 PM Software Development: RE: Enable DDR ECC in Am62A processor
- Attached 2 patches for u-boot and 1 patch for the kernel.
Most of these changes you and Mike have already talked about. I think attachment:0002-mitysom-62ax-hack-Reduce-4GB-size-for-ECC.patch is likely the part your missing.
Also ... - JC 02:20 PM Software Development: RE: Enable DDR ECC in Am62A processor
- Thanks Rajkumar, I agree. I'll look into it today.
- RD 04:22 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Jonathan,
Thank you for the clarification.
From what I understand, the DDR setup code dynamically detects the RAM size and initializes the DDR during the U-Boot phase. When ECC is enabled, a portion of memory (around 1/9th) is r...
05/13/2025
- JC 09:25 PM Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Rajkumar Dumala wrote in message#6940:
> Hi Mike,
> ...
Note per "PCN20250509000":https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Errata_and_Module_Product_Change_Notifications the AM62A you have may be set to 1.25... - MW 09:29 AM Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Hi Rajkumar,
It's not clear why there would be a difference between the two. It's the same processor / frequency design.
You might try and disable all of the peripherals you don't intend to use in the device tree you are using, as... - RD 07:28 AM Software Development: RE: Debian SDK Not booting in am62p (Am62x dev kit)
- Hi Mike,
I was on leave for the past four days, so I wasn't able to communicate.
When we tested on the TI EVM, the behavior was slightly better, and we were able to achieve 800 Hz.
Thank you,
Rajkumar.
- JC 04:48 PM Software Development: RE: Enable DDR ECC in Am62A processor
- Sorry guys. Ecc doesn't work with the current u-boot code.
The issue is my ddr setup code which dynamically sets up the ddr based on ddr size. The code needs to reduce the max size when ecc is enabled.
I have some hard coded test c... - MW 02:21 PM Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Raj,
Does it work on the TI EVM? The reason I ask is that the EVM has 8 GB of memory. I just want to make sure it's memory size and not something with the IPC / DSP comms and enabling ECC that is the problem.
-Mike
- RD 02:01 PM Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Mike,
I don't understand why it's not working, even though all the reserved regions seem to be within the valid memory range.
@@[ 0.000000] Reserved memory: created CMA memory pool at 0x00000000c0000000, size 256 MiB
[ 0.00... - MW 12:11 PM Software Development: RE: Enable DDR ECC in Am62A processor
- Hi Rajkumar,
From this link:
https://support.criticallink.com/redmine/projects/mitysom_am62x/wiki/Enabling_DDRSS_ECC
The maximum memory address is approximately 0xFFFFFFFF * 8 / 9 ~= 0xE38E38E2
It looks like the maximum CMA s... - RD 10:42 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Hello,
It was my mistake—I shared the wrong screenshot earlier. You can find the correct one attached with this message.
Thank you,
Rajkumar - RD 10:38 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Hello Mike,
I reduced the CMA size to 512 MiB; however, the issue remains the same.I am providing the image for your reference.
Thank you,
Rajkumar.
- MW 09:37 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Well. Sorry it only goes up to 0xF0000000. But that still may be too high.
- MW 09:36 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Hello,
When you enable ECC in LPDDR4, you reduce the maximum amount of addressable memory available to the device. IT uses some of the 4 GB to hold the ECC data.
The CMA settings I am seeing above include a 576 MB (assuming 0x2000... - RD 07:49 AM Software Development: RE: Enable DDR ECC in Am62A processor
- Just to add to the above point:
In the boot log, it shows that ECC is enabled, and I am able to run some test cases as mentioned in the TI documentation using U-Boot (manual boot mode).
Thank you. - Hello there,
We are using the MitySOM-AM62x Devkit with the AM62A System on Module (SoM), which includes 4 GB of LPDDR4 (with inline ECC).
As part of SDL, we enabled ECC in the R5 MSRAM (512 KB) it is working fine . After that, I e...