Activity
From 05/13/2025 to 06/11/2025
06/11/2025
- TR 06:00 AM Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- Thank you
Will update if anything else comes up.
06/10/2025
- JC 03:07 PM Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- Thejas Raj wrote in message#6981:
> Hi,
> ...
First please note that the R6/T9 pins will be 1.8V logic level. If your device is 3.3V logic level you will need a voltage translator similar to U5 on the devkit.
> Can you give us the ... - TR 10:04 AM Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- Hi,
So we were able to interface i2c5 of the evk with our pca 9535 i2c device.
As of now we also require i2c4 of the evk/som whose scl and sda are currently muxed to gpio7_3 (R6) and gpio7_4 (T9) respectively.
Can you give us the...
06/05/2025
- JC 01:53 PM Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- Okay sounds good
- TR 08:55 AM Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- Sorry for the late reply.
We were able to interface the pca9535 after adding the respective nodes for it in the i2c5 bus configuration in the am57xx-mitysom-baseboard.dts file.
Will update if anything else comes up.
Thank you
06/03/2025
- JC 06:43 PM Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- > even when data is coming from pca9535. I suppose the 20 1 column should show 21, but it is not coming up.
What does this mean? How is data coming from the pca9535 if you cannot talk to it?
> ...
What are the address A0, A1, A2 pin... - TR 03:48 PM Software Development: RE: Interfacing pca9535 with arm using i2c expanders (J5)(i2c5)
- correction: the extension is J4
- Hello,
We are trying to interface external pca9535 with the evk via the i2c5 bus. We'll be using the J5 extension on the board to do so.
As far as I know, 0x21 is the memory address that is supposed to be used by pca9535 but i2cdet...
05/30/2025
- JC 02:57 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Thejas Raj wrote in message#6973:
> Hi,
> ...
Please clone the u-boot and kernel source separately using git. - TR 05:55 AM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Hi,
Thank you for your reply.
And can you give me the path to the u-boot device tree in the yocto environment. The boards/cl directory mentioned in the u-boot wiki that you just provided, especially.
05/29/2025
- JC 02:00 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Note if you are developing a custom board, we'd be happy to do a schematic/layout review as well. Those can be emailed to info@criticallink.com
- JC 01:57 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Unfortunately TI's guidance at least for SDK 6, is that the majority of pinmuxing must be done in u-boot while the IO's are in isolation mode... Setting up the pinmux in u-boot is covered in this following wiki page.
https://support.... - Hi,
We have a yocto source built following the arm development wiki and a working base image.
We are trying to change the pin mux settings some of the peripherals like gpio through the dts files. But cant seem to find anything reg...
05/26/2025
- MW 10:47 AM Software Development: RE: Programming FPGA through JTAG and High speed data transfer support
- Hi Shankar,
It is a US holiday today, I will add some documentation for programming via JTAG (at least a wiki page) first thing tomorrow.
In the meantime, you should be able to use any AMD / Xilinx approved POD, but you will need a... - Hello everyone,
We are currently working on a project using the MitySOM-AM57X development board, and we would appreciate some guidance on programming the FPGA via JTAG. Could anyone kindly share the detailed procedure or point us to r...
05/23/2025
- SM 01:59 PM FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe
- Thanks mike for the quick response. I will look through these examples
- MF 01:45 PM FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe
- See link below for the FPGA example projects which include PCIe.
https://support.criticallink.com/redmine/projects/mitysom_am57x/wiki/FPGA_Example_Projects - We are using MitySOM-AM57(F) Development Kit for our development. Are there any examples provided to read and right to the FPGA via PCIe in the default BSP
which you are providing.
05/18/2025
- BS 06:47 PM PCB Development: RE: I/O voltage levels
- Hi Michael,
I would like to thank you for the continued support and prompt assistance you have extended to us.
As we proceed with the next steps, I would appreciate it if you could kindly share the detailed procedure for pr...