Activity
From 04/30/2025 to 05/29/2025
05/29/2025
- JC 02:00 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Note if you are developing a custom board, we'd be happy to do a schematic/layout review as well. Those can be emailed to info@criticallink.com
- JC 01:57 PM Software Development: RE: Configuring and editing the pinmux settings for AM57(F) dev kit through dts files.
- Unfortunately TI's guidance at least for SDK 6, is that the majority of pinmuxing must be done in u-boot while the IO's are in isolation mode... Setting up the pinmux in u-boot is covered in this following wiki page.
https://support.... - Hi,
We have a yocto source built following the arm development wiki and a working base image.
We are trying to change the pin mux settings some of the peripherals like gpio through the dts files. But cant seem to find anything reg...
05/26/2025
- MW 10:47 AM Software Development: RE: Programming FPGA through JTAG and High speed data transfer support
- Hi Shankar,
It is a US holiday today, I will add some documentation for programming via JTAG (at least a wiki page) first thing tomorrow.
In the meantime, you should be able to use any AMD / Xilinx approved POD, but you will need a... - Hello everyone,
We are currently working on a project using the MitySOM-AM57X development board, and we would appreciate some guidance on programming the FPGA via JTAG. Could anyone kindly share the detailed procedure or point us to r...
05/23/2025
- SM 01:59 PM FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe
- Thanks mike for the quick response. I will look through these examples
- MF 01:45 PM FPGA Development: RE: MitySOM-AM57F communicating to FPGA via PCIe
- See link below for the FPGA example projects which include PCIe.
https://support.criticallink.com/redmine/projects/mitysom_am57x/wiki/FPGA_Example_Projects - We are using MitySOM-AM57(F) Development Kit for our development. Are there any examples provided to read and right to the FPGA via PCIe in the default BSP
which you are providing.
05/18/2025
- BS 06:47 PM PCB Development: RE: I/O voltage levels
- Hi Michael,
I would like to thank you for the continued support and prompt assistance you have extended to us.
As we proceed with the next steps, I would appreciate it if you could kindly share the detailed procedure for pr...
05/12/2025
- MW 01:37 PM PCB Development: RE: I/O voltage levels
- Hi Shankar,
Take a look at our PCIE / DMA example on our git server:
https://support.criticallink.com/gitweb/?p=mitysom-am57x-ref.git;a=tree;f=fpga/pcie_dma_example;hb=0e1b86410b434ec44afb98d9959deaee252902c0
The project should ... - BS 12:25 PM PCB Development: RE: I/O voltage levels
- Hi Michael,
Thank you for your response.
We are initiating FPGA development on the MitySOM-AM57X development board
using Vivado. We are currently seeking the FPGA pin mapping details for the
PCIe interface to the ARM processor. We ...
05/05/2025
- MW 12:12 PM PCB Development: RE: I/O voltage levels
- The SOM ties the following AM57x voltage IO domains to 1.8V. You will need to use level shifters on your board to get to +3.3V IO interfaces.
VDDSHV1
VDDSHV2
VDDSHV3
VDDSHV4
VDDSHV6
VDDSHV7
VDDSHV9
VDDSHV10
VDDSHV11
VDDSHV... - BS 12:01 PM PCB Development: RE: I/O voltage levels
- Hello Mike,
Thank you for your swift and helpful response.
We are planning to use I2C3, I2C4, and I2C5 interfaces of AM57XX in our design.
Kindly correct us if we are mistaken — as we understand from the documentatio... - MW 11:41 AM PCB Development: RE: I/O voltage levels
- Hello,
You should use level shifters to shift up to 3.3V. Do not pull the I2C pins directly to 3.3V or modify the SOM.
Our Dev Kit schematic uses TCA9803DGKR, but there are several shifters avialable that should work.
Which I... - In the data sheet of MITY-SOM_AM57F SOM board page 4, it is mentioned that the AM57XX MFIOs are operating at 1.8V level except mmc1 pins. We have an I2C connections that goes to AM57XX processor, we need the voltage levels of the I2C pin...