Activity

From 06/18/2023 to 07/17/2023

TC 02:15 PM PCB Development: RE: Is the USB SS connection correct?: Thanks, Jon!
Tom Thomas Catalino
JC 02:01 PM PCB Development: RE: Is the USB SS connection correct?: Thanks for pointing that out. Posted updated schematics and noted them on this new wiki page. https://support.criticallink.com/redmine/projects/mitysom_am57x/wiki/Development_Kit_Revision_Information Jonathan Cormier
SS 08:49 AM PCB Development: RE: Is the USB SS connection correct?: Hi,
Can you please share the schematic design file location in the website. I am getting old schematic design from the "files" link.
With regards
Sandeep S Sandeep Sivadas

JC 01:05 PM PCB Development: RE: Is the USB SS connection correct?: Here is a snapshot from the devkit design in case it helps. The full schematic is available in the files section.
!clipboard-202307140903-bbh2e.png!
!clipboard-202307140904-01axr.png!
Jonathan Cormier
MW 09:35 AM PCB Development: RE: Is the USB SS connection correct?: Hello,
I had edited my previous post to correct. Yes it is:
Correct: AM572x (USB_TXN/P0)
The 80-001317RH-5_SCH_RevA.PDF should properly connect the USB-3. You can assume it is OK.
-Mike Michael Williamson
MF 01:19 AM PCB Development: RE: Is the USB SS connection correct?: > MitySOM-AM57 System on Module (J3, J14)) ~ HD3SS3220IRNHR (U12) ~ USB TypeC (J13) connection (SSTX_P / _N, SSRX_P / _N) is there any problem with the circuit diagram below?
> ...
Can I assume that aside from the pin names, there are n... Masayoshi Furuta

MF 10:39 PM PCB Development: RE: Is the USB SS connection correct?: > Pin 33/35 are connected to AC11/AD11 on the *FPGA* (USB_TXN/P0), with AC coupling (DC blocking) capacitor.
Will this one also be corrected as follows?
Incorrect: FPGA (USB_TXN/P0)
Correct: AM572x (USB_TXN/P0)
Masayoshi Furuta
JC 02:22 PM PCB Development: RE: Is the USB SS connection correct?: Correction: Replace FPGA with ARM Jonathan Cormier
MW 10:25 AM PCB Development: RE: Is the USB SS connection correct?: Hi Masayoshi,
It looks like there is an error in the datasheet.
Pin 33/35 are connected to AC11/AD11 on the FPGA (USB_TXN/P0), with AC coupling (DC blocking) capacitor.
Pin 27/29 are connected to AF12/AE12 (USB_RXN/P0) as straig... Michael Williamson
MF 06:39 AM PCB Development: Is the USB SS connection correct?: The J3Pin-Out (Table 7) of the MitySOM-AM57 System on Module data sheet describes the USB3.0 SuperSpeed terminals as follows.
Pin27 AC11 USB1_SSRX_N
Pin29 AD11 USB1_SSRX_P
Pin33 AF12 USB1_SSTX_N(2)
Pin35 AE12 USB1_SSTX_P(2)
... Masayoshi Furuta

TC 01:57 PM PCB Development: RE: about MECHANICAL INTERFACE in AM57x DataSheet: Thank you for pointing this out. We will repair the figure references in the next revision of the datasheet. In both cases the erroneous reference is to the figures directly below the text where the error appears. Thomas Catalino
MF 12:47 AM PCB Development: about MECHANICAL INTERFACE in AM57x DataSheet: https://www.criticallink.com/wp-content/uploads/60-000055-MitySOM-AM57_datasheet.pdf
On P29 and P31 of the DataSheet.
You find "Error! Reference source not found."
Please update document.
Masayoshi Furuta

MW 08:07 PM PCB Development: RE: Unconnected pins, board dimensions and hole positions: Hello.
1. Generally speaking, all of the MFIO pins are direct connects to the AM57xx CPU device and if they are unused in your design it is safe to leave them not connected. The Ball numbers are included in the table and can be cross... Michael Williamson
TC 06:51 PM PCB Development: Unconnected pins, board dimensions and hole positions: Posting on behalf of customer:
1.The J1 and J3 connectors of MitySOM-AM57 are described as “MFIO” for “Type”.
"If this pin is not used, can it be left unconnected?"
(Table 6, Table 7 in MitySOM-AM57_datasheet.pdf)
2.Is it okay... Thomas Catalino

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Mity CPU Platforms » MitySOM-AM57X