Activity
From 07/10/2026 to 08/08/2026
07/13/2026
- EH 01:13 PM FPGA Development: RE: Not being able to Make jic
- Good morning,
I have readded the PCIe RP IP, but it I still can't regenerate/update the a5e because the tool complaints about the hps emif.
Thank you,
Eleonora
07/10/2026
- MF 03:55 PM FPGA Development: RE: Not being able to Make jic
- I believe the PCIe RP IP needs to be regenerated / re-added if you switch between production silicon or R0 silicon so that may be your issue with the PCIe IP.
The speed grade 4 SOM is capable of 1066 MHz DDR while the speed grade 6 SB... - EH 03:36 PM FPGA Development: RE: Not being able to Make jic
- Yes,
The actual label on the SOM is A5ED-B64-144-SRC-X, but the box says A5ED-B64-144-SRI-X
I checked the SBC also using jtagconfig and it came back as
1) USB-BlasterII [USB-1]
4BA06477 ARM_CORESIGHT_SOC_600
0364F0DD A5E(C0... - MF 02:57 PM FPGA Development: RE: Not being able to Make jic
- Eleonora,
Can you read the label / sticker that is on the SOM module? I believe the device you actually have installed into the development kit is the *A5ED-B64-144-SRC-X* and not *A5ED-B64-144-SRI*. I think this is where the confusio... - EH 01:46 PM FPGA Development: RE: Not being able to Make jic
- It actually came back with different FPGA - the one that you have
jtagconfig
1) USB-BlasterII [USB-1]
4BA06477 ARM_CORESIGHT_SOC_600
0364F0DD A5E(C065BB32AR0|D065BB32AR0)
I'll change the devise and start over.
I'll let...