Activity

From 05/10/2026 to 06/08/2026

MF 07:22 PM Software Development: RE: make_sd.sh doesn't take command line parameters: Hi Max,
I just wanted to follow up and tell you that I have published a new DMA reference design to our repository and updated the Wiki page [[A5E-DMA-Example]]
Let me know if you have any questions regarding the updated design.
... Mike Fiorenza

MF 03:31 PM Software Development: RE: cl_msgdma.ko has the wrong version: Hi Samuel,
We plan to integrate this kernel module into our kernel in the near future, so this would be handled automatically for the end user.
However, until then you could explore options such as adding a recipe into the Yocto bu... Mike Fiorenza

SP 10:03 PM Software Development: RE: cl_msgdma.ko has the wrong version: This way works to make a compatible version of cl_msgdma.ko. (/) :D
Is there a way to build it inside the docker container at the same time we build the file system.
https://support.criticallink.com/redmine/projects/mitysom_a5/wiki/... Samuel Paul
MF 07:28 PM Software Development: RE: cl_msgdma.ko has the wrong version: Hi Samuel,
The Wiki instructions say to deploy the compiled kernel and kernel modules to the SD card as well. This way you ensure that all binaries are in sync and the vermagic matches.
You can however try to work around this by ma... Mike Fiorenza
SP 06:55 PM Software Development: cl_msgdma.ko has the wrong version: When I try to insert the cl_msgdma kernel module I get the following message.
root@mity-a5e:~# insmod cl_msgdma.ko
[426692.912739] cl_msgdma: version magic '6.12.33-g511c86cb48bf SMP preempt mod_unload aarch64' should be '6.12.33-yo... Samuel Paul

MF 03:43 PM Software Development: RE: make_sd.sh doesn't take command line parameters: Hi Max,
As mentioned in the "HPS/FPGA Shared Memory thread":https://support.criticallink.com/redmine/boards/75/topics/7293 the data errors you saw were caused by a bug in my xor data generator core. This will be resolved in our next r... Mike Fiorenza
MK 03:32 PM Software Development: RE: make_sd.sh doesn't take command line parameters: Hello Zach,
We are back to test DMA example design.
Do you have any update regarding the failure that we saw??
Thanks,
Max Maxim Kanevsky

MF 02:44 PM FPGA Development: RE: HPS/FPGA shared external memory: Hi Max,
Just to make sure we're aligned on the DMA example — what it demonstrates is really the same use case you're after: exchanging data between the FPGA and the ARM through HPS DDR. The example uses the F2H (FPGA-to-HPS) path. The... Mike Fiorenza
MK 01:42 PM FPGA Development: RE: HPS/FPGA shared external memory: Sorry, forgot to mention, as you suggested, ve tried first DMA example design and we tried to run it. But for now we are interesting in shared memory access, so that's why we are trying FPGA to SDRAM Maxim Kanevsky
MK 01:40 PM FPGA Development: RE: HPS/FPGA shared external memory: Hello again,
I've created a project based on mitysom-a5e-ref-base project.
We made following modifications:
- we added FPGA to SDRAM Subordinate Bridge into HPS Subsystem
- we added AVMM to AXI4 Bridge (because all of our modules a... Maxim Kanevsky

MW 05:09 PM PCB Development: RE: HVIO Speed at 3v3: Hi Naufal,
The "Agilex-5 datasheet":https://docs.altera.com/r/docs/813918/current/agilextm-5-fpgas-and-socs-device-data-sheet/i/o-pll-specifications specifies the Input clock frequency source from HVIO clock input at a max of 156.25 M... Michael Williamson
NA 04:45 PM PCB Development: HVIO Speed at 3v3: Hello,
I'm working on an FMC PCB that will interface with the MitySBC-A5E. The board contains an ADV7611 HDMI receiver and an ADV7513 HDMI transmitter, both of which have decoded pixel bus inputs/outputs at 3v3 logic levels. The pixel... Naufal Ahmad

MK 06:20 PM FPGA Development: RE: Signal Tap not working: Hello Mike, thanks a lot. Yes, not it is working
Max Maxim Kanevsky
MF 04:51 PM FPGA Development: RE: Signal Tap not working: Hi Max,
As shown on the right side of your screenshot, you do not have the correct device selected. You need to select Device: @2 which is the FPGA. @1 device is the ARM.
Let me know if changing that drop box resolves your issue.
... Mike Fiorenza
MK 04:40 PM FPGA Development: Signal Tap not working: Hello !!!
We are using mitysom-a5e-ref-base as a reference and we've added FPGA2SDRAM port to HPS and some Avalon Memeory-Mapped generator to initiate some traffic from FPGA to the SDRAM. We also addd Signal Tap to see if the generator ... Maxim Kanevsky

Also available in: Atom

Mity CPU Platforms » MitySOM-A5