Mity CPU Platforms » MitySOM-A5

09/03/2025

TC 01:23 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?

Hello Maxim -
Just getting back to you on our plan for a reference project. The reference project that we will be putting together will be root port, and not endpoint. So I don't believe it will support your use case. We will continu... Thomas Catalino

09/02/2025

MW 07:36 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?

Hello Maxim,
You only need 1 100 MHz reference clock to run the PCIe transceiver blocks. You should be able to use either pair (G16/G17 or G12/G13), just make sure you specify the correct pins in the quartus project. Our design requ... Michael Williamson

MF 02:08 PM FPGA Development: RE: Fail to program device

As shown by the log file it appears that you do not have the ARM toolchain installed. It is failing to compile the bootloader code. Please follow this wiki to install the GCC-ARM-11.2 toolchain.
https://support.criticallink.com/redmin... Mike Fiorenza

08/29/2025

KM 08:36 PM PCB Development: RE: PCIe connection to Computer MB

Hello,
yes, actually it is worse than that.. the FPGA can only tolerate about 10mA, and must be less than 1.2V during power up ... so best to add 100 ohm pull-down to both these signals.
thanks,
Keith.
Keith Murison

MW 06:50 PM PCB Development: RE: PCIe connection to Computer MB

Hi Keith,
I don't think you can drive it in the FPGA (PCIe needs to be up fairly quickly and may need to be there before the FPGA fully configures).
I would just tie or (use on a 100 ohm as you suggest) both lines to ground and ens... Michael Williamson

KM 12:36 AM PCB Development: RE: PCIe connection to Computer MB

Hi,
Actually, there is another issue, in EP mode, the Presecence signals, PRSNT2_*X1*# and PRSNT2_*X4*# need to be pulled-down by the Target/EP device,
however, these signals are pulled-up on the SoM, for the PCIE_X4_PRSNT2n_3V3 si... Keith Murison

MK 06:25 PM FPGA Development: RE: What is the recommended version of Quartus for MitySOM_A5?

Hello Tom,
Thanks for the explanation.
Me and Keith, we are working together. We've ordered a cable (PCIe edge on both ends and cross-connect - to make it possible to connect the Mity Carrier board as PCIe End-Point)
I saw also a ki... Maxim Kanevsky

MK 06:13 PM FPGA Development: RE: Fail to program device

Mike, please see attached log of the compilation Maxim Kanevsky

MK 06:07 PM FPGA Development: RE: Fail to program device

Hello Mike,
No I didn't made any changes. I removed everything. I clone again, navigate to directory and run command "make jic". It run again and again no files as expected Maxim Kanevsky