Mity CPU Platforms » MitySBC-Agilex5

03/25/2026

EH 05:53 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5

Thank you Mike.
We currently have SBC and SOM Dev kit. We were told that they are equivalent from FPGA connections point of view, but I found out that's not completely correct.
I need the schematic to figure out which FPGA pins and how... Eleonora Haralanova

03/24/2026

MW 09:37 AM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5

Hi Eleonora,
I was advised that you are working with our "MitySOM-A5E":https://www.criticallink.com/product/mitysom-a5e-standard-dev-kit/ product vs. our "MitySBC-A5E":https://www.criticallink.com/product/mitysbc-a5e-single-board-comp... Michael Williamson

03/12/2026

MF 09:46 PM FPGA Development: RE: building FPGA and bootloader

Eleonora,
Our Makefile is currently configured to support Linux. So installing Quartus inside of WSL or a Linux VM would make following our Wiki instructions easier.
That said, you could try the following to convert your JIC the... Mike Fiorenza

EH 07:00 PM FPGA Development: building FPGA and bootloader

Hi,
I have Quartus Pro 25.3 with the fix, but it's installed in Windows. If I compile the ref-base project in Windows, I get sof file and when I try to convert it to jic - I get an error that the bootloader configuration is missing and ... Eleonora Haralanova

03/03/2026

MW 08:51 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5

Hi Eleonora,
Are you trying to run EP or RP?
The GBTCLK0_M2C_P/N on FMC D4/D5 is run to REFCLK_GSTR4B_CH1p/n (AV16 AV21) of the FPGA.
The GBTCLK1_M2C_P/N on FMC B20/B21 is run to REFCLK_GSTR4A_CH1p/n (BB16 BB21) of the FPGA.
... Michael Williamson

EH 08:26 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5

Thank you, Mike.
I was asking about the schematic, because I don't have information about all the pins that are connected on the PFGA. We are working with Arrow, so I'll ask them for schematic, but can you answer few more questions abo... Eleonora Haralanova

03/02/2026

MW 08:14 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5

Hello Eleonora,
To confirm, are you using the MitySBC hardware? If so then the three possible banks for PCIe x4 would be:
Bank GTSL1B (M.2 Connector)
Bank GTSR4B (FMC DP0->DP3)
Bank GTSR4A (FMC DP5->DP7 .... reversed connectio... Michael Williamson

EH 03:24 PM FPGA Development: Where can I find the schematic for MitySBC_Agilex5

Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the... Eleonora Haralanova

02/26/2026

TC 02:58 PM Software Development: RE: Eclipse Application

Got it thank you!
Tom Thomas Catalino

MF 02:52 PM Software Development: RE: Eclipse Application

This question was posted and answered on thread: https://support.criticallink.com/redmine/boards/72/topics/7175
If you have any further questions regarding this topic don't hesitate to reach out. Mike Fiorenza