Activity
From 02/11/2026 to 03/12/2026
03/12/2026
- MF 09:46 PM FPGA Development: RE: building FPGA and bootloader
- Eleonora,
Our Makefile is currently configured to support Linux. So installing Quartus inside of WSL or a Linux VM would make following our Wiki instructions easier.
That said, you could try the following to convert your JIC the... - Hi,
I have Quartus Pro 25.3 with the fix, but it's installed in Windows. If I compile the ref-base project in Windows, I get sof file and when I try to convert it to jic - I get an error that the bootloader configuration is missing and ...
03/03/2026
- MW 08:51 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Hi Eleonora,
Are you trying to run EP or RP?
The GBTCLK0_M2C_P/N on FMC D4/D5 is run to REFCLK_GSTR4B_CH1p/n (AV16 AV21) of the FPGA.
The GBTCLK1_M2C_P/N on FMC B20/B21 is run to REFCLK_GSTR4A_CH1p/n (BB16 BB21) of the FPGA.
... - EH 08:26 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Thank you, Mike.
I was asking about the schematic, because I don't have information about all the pins that are connected on the PFGA. We are working with Arrow, so I'll ask them for schematic, but can you answer few more questions abo...
03/02/2026
- MW 08:14 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5
- Hello Eleonora,
To confirm, are you using the MitySBC hardware? If so then the three possible banks for PCIe x4 would be:
Bank GTSL1B (M.2 Connector)
Bank GTSR4B (FMC DP0->DP3)
Bank GTSR4A (FMC DP5->DP7 .... reversed connectio... - Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the...
02/26/2026
- TC 02:58 PM Software Development: RE: Eclipse Application
- Got it thank you!
Tom - MF 02:52 PM Software Development: RE: Eclipse Application
- This question was posted and answered on thread: https://support.criticallink.com/redmine/boards/72/topics/7175
If you have any further questions regarding this topic don't hesitate to reach out.
02/19/2026
- MW 07:15 PM Software Development: RE: Application Debug
- What are you trying to debug?
If it is an application space program, I would recommend starting with gdb / gdbserver and connecting via a cross tools IDE over the network.
We have instructions for doing this using VS Code on the li... - What would be the best solution for an application debug?
02/12/2026
- BH 03:19 PM Software Development: RE: Eclipse Application
- Thank you this is very helpful, What is the best was to debug that you recommend?
02/11/2026
- MF 10:31 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FPGA_CLKIN_P.
So FPGA_CLKIN_P would go to the EMIF IP for its internal PLL that gets spun up to clock the DDR interface... - MF 10:24 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (Clocks the ARM, peripheral clocks, etc) also is where the hps_user0_clk comes from
The rest of the clocks come from tw... - EH 10:12 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able to build all 3 projects.
About adding a IOPLL as a reference clock for the DDR controller - what are the actual clocks... - MF 09:10 PM FPGA Development: RE: 25.3 projects can't get recompiled
- Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this reference design project checked out in a long directory path? Looking online this may be a common Windows problem where ... - Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get errors and was not successful. For the Emif project, during analysis and synthesis I get the following:
Error(16827)...