Mity CPU Platforms » MitySBC-Agilex5

03/02/2026

MW 08:14 PM FPGA Development: RE: Where can I find the schematic for MitySBC_Agilex5

Hello Eleonora,
To confirm, are you using the MitySBC hardware? If so then the three possible banks for PCIe x4 would be:
Bank GTSL1B (M.2 Connector)
Bank GTSR4B (FMC DP0->DP3)
Bank GTSR4A (FMC DP5->DP7 .... reversed connectio... Michael Williamson

EH 03:24 PM FPGA Development: Where can I find the schematic for MitySBC_Agilex5

Hello,
I'm trying to instantiate 3 PCIe Gen3 x4 lanes IPs in the FPGA but can't figure out which pins are available to use. From the datasheet - the M2 connector is one, then the FMC has another 4 lanes, but I don't see where to put the... Eleonora Haralanova

02/26/2026

TC 02:58 PM Software Development: RE: Eclipse Application

Got it thank you!
Tom Thomas Catalino

MF 02:52 PM Software Development: RE: Eclipse Application

This question was posted and answered on thread: https://support.criticallink.com/redmine/boards/72/topics/7175
If you have any further questions regarding this topic don't hesitate to reach out. Mike Fiorenza

02/19/2026

MW 07:15 PM Software Development: RE: Application Debug

What are you trying to debug?
If it is an application space program, I would recommend starting with gdb / gdbserver and connecting via a cross tools IDE over the network.
We have instructions for doing this using VS Code on the li... Michael Williamson

BH 06:29 PM Software Development: Application Debug

What would be the best solution for an application debug? Brady Heater

02/12/2026

BH 03:19 PM Software Development: RE: Eclipse Application

Thank you this is very helpful, What is the best was to debug that you recommend? Brady Heater

02/11/2026

MF 10:31 PM FPGA Development: RE: 25.3 projects can't get recompiled

Eleonora,
If you are asking what clock to drive your IOPLL clock with, you should be able to use the same clock FPGA_CLKIN_P.
So FPGA_CLKIN_P would go to the EMIF IP for its internal PLL that gets spun up to clock the DDR interface... Mike Fiorenza

MF 10:24 PM FPGA Development: RE: 25.3 projects can't get recompiled

Eleonora,
Glad to hear you were able to build the projects!
HPS_CLK_25MHz is a 25 MHz oscillator for the HPS (Clocks the ARM, peripheral clocks, etc) also is where the hps_user0_clk comes from
The rest of the clocks come from tw... Mike Fiorenza

EH 10:12 PM FPGA Development: RE: 25.3 projects can't get recompiled

Thank you, Mike, for your reply.
The problem really was the Windows inability to works with long paths. I was able to build all 3 projects.
About adding a IOPLL as a reference clock for the DDR controller - what are the actual clocks... Eleonora Haralanova

MF 09:10 PM FPGA Development: RE: 25.3 projects can't get recompiled

Hi Eleonora,
Are you using Quartus Pro 25.3 version exactly? If so, do you also happen to be on Windows and this reference design project checked out in a long directory path? Looking online this may be a common Windows problem where ... Mike Fiorenza

EH 06:46 PM FPGA Development: 25.3 projects can't get recompiled

Hello,
I'm trying to recompile any of the design for 25.3 and even after installing the patch for Quartus Pro, I get errors and was not successful. For the Emif project, during analysis and synthesis I get the following:
Error(16827)... Eleonora Haralanova

02/09/2026

MF 08:14 PM Software Development: RE: Eclipse Application

Hi Brady,
In order to build an ARM application for the Agilex 5 on your PC you first need to obtain a toolchain so that you can cross compile the application. The ARM toolchains can be found here: https://developer.arm.com/downloads/-... Mike Fiorenza

BH 07:16 PM Software Development: Eclipse Application

What is the best was to set up an environment preferable eclipse to build an application. Brady Heater