Activity

From 12/23/2025 to 01/21/2026

EH 02:36 PM MitySBC-Agilex5 FPGA Development: RE: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging: Thank you. Eleonora Haralanova

MW 05:03 PM MitySBC-Agilex5 FPGA Development: RE: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging: Hi Eleonora,
There was a major bug in quartus related to timestamps in January (starting 1/10). You likely need to apply a patch for this to be resolved.
See this link:
https://community.altera.com/kb/knowledge-base/why-do-i-un... Michael Williamson
EH 04:37 PM MitySBC-Agilex5 FPGA Development: hps_sybsys.qsys not getting validated in platform Designer and Quartus hanging: Hello,
I downloaded the Example projects for Quartus Pro 25.3, copied and renamed the base project and just tried to compile without any changes. I didn't even open the qsys. Quartus first validated a5e.qsys and then moved to validate h... Eleonora Haralanova

MF 08:37 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5CSX (5CSX-H6-42A-RI) stops at “Deasserting all peripheral resets” — request for guidance: The RMA on this thread has been handled and completed.
For anyone looking for resolution to the question about the encrypted FPGA bitstream, see the following forum post: https://support.criticallink.com/redmine/boards/47/topics/7107 Mike Fiorenza

SG 04:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX: Hi John,
Glad you were able to work through the stuff I described and get things working, you're welcome!
Yes, great observation. Lines 549-562 are the I/O available on the partial header, while the rest are available on the full h... Seth Graber
JI 12:28 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX: Hi Seth,
I found all the stuff that you described below and have started to study the .vhd file. Thanks. I also got bit 30 to work as described.
That said, it appears (from the .vhd file, lines 549-562) that those I/Os are only avai... John Iannuzzi

SG 02:29 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX: Hi John,
Apologies, I believe I sent you an internal link. The schematic you have is correct and has the same connections for the HSMC connectors. They can be found on page 6. Hope this helps, apologies once again for any confusion!
... Seth Graber
JI 02:25 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX: I have this schematic...
80-000578RC-10_SCH_RevB.PDF John Iannuzzi
JI 12:47 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX: Hi Seth,
I'll take a look. Also, I get a page load error with the 1st link :
https://svnsrv.syr.criticallink.com/svn/production/Current/80-Assemblies/80-000578RC-11_RevA%20MitySOM-5CSx%20Dev%20Board%20PCA/80-000578RC-11_RevA_SCH.PDF#p... John Iannuzzi

SG 04:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX: Hi John,
Thank you, happy (belated) Holidays to you as well! I appreciate your patience for a response as I was out of office. Glad you were able to rebuild the device tree and get the RGB scripts to work.
I went ahead and took a l... Seth Graber

JI 04:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX: Hi Seth,
Happy Holidays!
Ok, I was able to rebuild the device tree as you instructed and got it all to work, including the RGB scripts. It appears now I have a fully operational sd card image.
Back to the FPGA GPIO. So I connected... John Iannuzzi

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