Mity CPU Platforms

01/06/2026

SG 02:29 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX

Hi John,
Apologies, I believe I sent you an internal link. The schematic you have is correct and has the same connections for the HSMC connectors. They can be found on page 6. Hope this helps, apologies once again for any confusion!
... Seth Graber

JI 02:25 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX

I have this schematic...
80-000578RC-10_SCH_RevB.PDF John Iannuzzi

JI 12:47 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX

Hi Seth,
I'll take a look. Also, I get a page load error with the 1st link :
https://svnsrv.syr.criticallink.com/svn/production/Current/80-Assemblies/80-000578RC-11_RevA%20MitySOM-5CSx%20Dev%20Board%20PCA/80-000578RC-11_RevA_SCH.PDF#p... John Iannuzzi

01/05/2026

SG 04:34 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX

Hi John,
Thank you, happy (belated) Holidays to you as well! I appreciate your patience for a response as I was out of office. Glad you were able to rebuild the device tree and get the RGB scripts to work.
I went ahead and took a l... Seth Graber

12/28/2025

JI 04:14 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Building the MitySOM-5CSX

Hi Seth,
Happy Holidays!
Ok, I was able to rebuild the device tree as you instructed and got it all to work, including the RGB scripts. It appears now I have a fully operational sd card image.
Back to the FPGA GPIO. So I connected... John Iannuzzi

12/19/2025

JC 10:55 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P PCB Development: RE: Fixture to Flash Image in Production

Holden Wozniak wrote:
> We are looking into ways to flash an image onto a SOM with eMMC in production.
> ...
DFU/snagboot was created for this scenario. We'd normally use our devkits to do factory programming but if you wanted to chan... Jonathan Cormier

HW 08:28 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P PCB Development: Fixture to Flash Image in Production

We are looking into ways to flash an image onto a SOM with eMMC in production.
Our current thought was to utilize DFU/Snagboot; we would provide the custom Yocto files and a script to run on a host PC. The host PC would be connected t... Holden Wozniak

12/17/2025

MF 08:29 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5CSX Dev Kit – USB OTG J401 not detecting USB devices

Hi Atef,
We just doubled checked on our side that the image you mentioned (Yocto (Poky 2.4.4, kernel 5.4.23-yocto-standard)) works as expected on the development kit.
Can you provide what type of USB OTG adapter you are using? We h... Mike Fiorenza

AF 04:41 PM MitySOM-5CSX Altera Cyclone V FPGA Development: MitySOM-5CSX Dev Kit – USB OTG J401 not detecting USB devices

Hello,
I am using a MitySOM-5CSX SOM on the standard Critical Link carrier (development kit) with Yocto (Poky 2.4.4, kernel 5.4.23-yocto-standard). I am trying to validate the USB OTG port J401 in host mode with a USB flash drive.
At b... Anonymous fpga

AF 07:18 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet PHY configuration and SSH access

Hello,
I am using a MitySOM-5CSX SOM on the standard Critical Link carrier (development kit) with Yocto (Poky 2.4.4, kernel 5.4.23-yocto-standard). I am trying to validate the USB OTG port J401 in host mode with a USB flash drive.
At b... Anonymous fpga

12/09/2025

DV 02:54 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet PHY configuration and SSH access

Hi Atef,
You should be able to do this via ethtool: Daniel Vincelette

AF 02:50 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet PHY configuration and SSH access

Hi Zach,
Could you please generate a Linux image for the 5CSX-H6-4YA based on the Linux image available at the following link (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki), but configured so that the Ethernet li... Anonymous fpga

MW 10:25 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet PHY configuration and SSH access

Hello,
For layout, the two groups you have outlined in your schematic snippet should be matched in length and ideally be on the same layer. The clocks should be separated from the data lanes by at least 5x trace width. We usually ... Michael Williamson

AF 08:47 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet PHY configuration and SSH access

Hi Zach,
Just a quick update on my side.
I am now able to communicate over Ethernet with our custom carrier board. However, in some cases I still observe data loss that results in dropped connections. My current suspicion is that thi... Anonymous fpga

AF 08:15 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Ethernet PHY configuration and SSH access

Hi Zach,
Thank you for your reply.
I ran ethtool eth0 | grep PHYAD on my system, and it confirms that the PHY is detected at address 3, as shown in the attached screenshot.
Could you please let me know if the Ethernet hardware section... Anonymous fpga