Mity CPU Platforms

01/23/2025

TI 08:40 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

What Dan showed you will start your application in the console... if your application exits (or you kill it with ctrl-c) you will be dropped to the command line, where you can restart your application or do other things. Tim Iskander

DV 06:55 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

Hello,
As Tim said an application launched through cron won't have access to standard in and out. What you could do is have getty(the login manager) autologin as root and use a .profile config file to launch your application.
Here ... Daniel Vincelette

BK 03:17 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

Hi,
I am currently working with the MitySOM Cyclone V device, which has only a single UART port. During boot-up, the boot logs are coming through this UART port. Once the system finishes booting, it prompts for a login. I am manually ... Bhardwaj Kotha

01/21/2025

TI 02:09 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: MTU increase Issue

If your program is reading from standard input, it will not be able to read anything when launched from cron. cron jobs have their standard input closed (or set to /dev/null, I don't remember exactly) and standard out will be shown in th... Tim Iskander

BK 01:03 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Issue with crontab

Hi,
MTU size issue was Resolved, and now I am facing with Crontab.
Actually I am running an application code on boot time and that way I am added the Executable lines on crontab. I am facing an issue with that after booting, my code ... Bhardwaj Kotha

MW 01:43 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

The Quartus Platform designer adds logic between the AXI bridge (not sure which bridge you are using) and your Avalon Memory slave interfaces to account for the fact that the AXI interface is command / response vs. a more standard / typi... Michael Williamson

BK 01:18 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board Logic Utilization Issue

Hi,
I am working on Data transmission from HPS to FPGA fabric, So i am used Avalon Memory Interface in Platform Designer. The issue is when i am not using that Avalon Memory interface it takes 10974/15880(69%) Logic Utilization(in ALM... Bhardwaj Kotha

01/20/2025

JC 07:51 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: RE: linux-cl-ti warnings (or perhaps notes?)

Thanks Nathan, I see this warning as well.
This warning is generated because we are setting the kernel defconfig in two places, in the machine config and the kernel recipe. We should remove the config from our machine conf as the one... Jonathan Cormier

NW 07:13 PM MitySOM-AM62, MitySOM-AM62A, & MitySOM-AM62P Software Development: linux-cl-ti warnings (or perhaps notes?)

WARNING: linux-cl-ti-6.6.32+git-r0 do_kernel_metadata: [NOTE]: defconfig was supplied both via KBUILD_DEFCONFIG and SRC_URI. Dropping SRC_URI entry /work/mitysom-am62x-ep00119/sources/meta-mitysom/recipes-kernel/linux/linux-cl-ti-6.6/k3/... Nathan Wright

MF 03:54 PM MitySOM-C10L FPGA Development: RE: Issue compiling MitySOM-C10L FPGA Reference Design

Hi Lucas,
Our example reference designs were implemented and tested with Quartus version 22.1. We would recommend that you use this version of Quartus (or newer). Additionally, make sure that your Quartus install has the Cyclone 10 LP... Mike Fiorenza

01/17/2025

LD 02:22 PM MitySOM-C10L FPGA Development: Issue compiling MitySOM-C10L FPGA Reference Design

Compilation of reference design fails. The issue seems to be that it does not find UART IP. Maybe it is because it is lacking definitions for 10CL080YU484I7G (see first error). Lucas Diodati