Activity
From 07/30/2024 to 08/28/2024
08/14/2024
- GG 01:48 AM MitySOM-C10GX Hardware Design: RE: JTAG Interface
- Hello,
Regarding the first question, unfortunately, the 2.5 V levels being used for the Max10 FPGA will not be compatible with MitySOM-C10G. The Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines states that for JTAG pins ...
08/09/2024
(Posted on behalf of a customer)
On my existing system, the Max10 FPGA has the USB Blaster interface that uses 2.5V JTAG levels that I also route to a CPLD on my board. From the MitySOM-C10G documentation, the 10G uses 1.8V JTAG L...
08/01/2024
- BK 12:52 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access
- Hi,
Actually that timing issues were resolved and ping performance also well as of now without packet loss. And now I am working fine with RGMII splitter connected to the HPS EMAC of latency 2 microseconds in my setup, I want to under...
07/31/2024
- TI 03:39 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Receive and send data using vlan tag
- Bhardwaj
There should be no devicetree changes necessary to use the VLAN feature of the Ethernet.
You verified that the 8021q module is loaded.
You should be able to create a VLAN interface and configure it from the shell and then add... - Hi,
I am working on ethernet using vlan. I had used the ip command to create the vlan after that some data sent from another PC having vlan and run receive code on board to receive data but we didn't get any data. when we try these e...