Mity CPU Platforms

06/27/2023

MF 06:13 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup

Eric,
https://www.intel.com/content/www/us/en/products/details/fpga/development-tools/quartus-prime/resource.html
Here is the link to the tools. Once you select the edition/platform that is applicable to you, you can change the ver... Mike Fiorenza

EN 05:43 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup

Thanks Mike.
That page filled in a couple of knowledge gaps for me.
I'm still struggling to find out where to get Quartus though.
Can you point me in the right direction?
I tried but was unsuccessful in getting the virtualbox... Eric Nelson

MF 03:41 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup

Eric,
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_fpga_181
This should be the build instructions for the project. Make sure to run the Intel Embedded Command Shell script to source the tools. This se... Mike Fiorenza

MF 05:35 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pin-muxing SPI

Eric,
Thanks for sharing! I wasn't sure if it supported arbitrary GPIO pins or not. Good to know!
- Mike Mike Fiorenza

EN 05:33 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pin-muxing SPI

Thanks Mike.
In case it's useful to someone else, I saw that the driver supports the use of "arbitrary GPIO pins":https://support.criticallink.com/gitweb/?p=linux-socfpga.git;a=blob;f=drivers/spi/spi-dw-mmio.c;h=447497e9124c922a4e3ecc... Eric Nelson

MF 03:36 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Pin-muxing SPI

Hi Eric,
Your assumptions are correct. To use the hard HPS SPI peripheral, you would use the signals you have highlighted in the attached image.
You could also not use the hard HPS SPI peripheral, and add a SPI controller into the FP... Mike Fiorenza

EN 05:27 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Toolchain bundles

Thanks Mike Eric Nelson

MF 03:43 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Toolchain bundles

Eric,
Use poky-glibc-x86_64-mitysom-image-base-cortexa9hf-neon-toolchain-2.4.4.sh which is under the Quartus 18.1 20201116 section.
Sorry for the confusion. I think the other two are legacy and should be removed.
- Mike Mike Fiorenza

06/26/2023

EN 09:51 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup

I'm also answering my first question (how to launch Quartus).
The executable name is quartus, and it seems that I don't have a proper installation. I followed instructions on Intel's site and seem to have a broken version 20.1.
In ... Eric Nelson

EN 04:01 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Project files and Quartus startup

I found the answer to the second question on this page:
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building_fpga_181
The reference projects are in this Git repository:
https://support.criticallink.com/git... Eric Nelson

EN 03:51 PM MitySOM-5CSX Altera Cyclone V Software Development: Project files and Quartus startup

I'm just getting started with a MitySOM-5CSX and
First off, this page says "launch quartus", and I'm not sure how.
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/System_Design_Overview
In my ~/intelFPGA tree... Eric Nelson

EN 03:53 PM MitySOM-5CSX Altera Cyclone V Software Development: Toolchain bundles

There are three poky toolchain bundles on this page, and two of them have the same name, "poky-eglibc-x86_64-mitysom-5csx-dev-kit-cortexa9hf-vfp-neon-toolchain-1.5.4.sh".
https://support.criticallink.com/redmine/projects/mityarm-5cs/f... Eric Nelson

06/23/2023

EN 11:54 PM MitySOM-5CSX Altera Cyclone V Software Development: Pin-muxing SPI

Hi all,
We'd like to make use of the SPI peripheral on the MitySOM-5CSx with at least two different chip-selects.
Is the use of the highlighted pins (SPIM0_SS0/SS1) the right approach?
I've worked with other SPI controller drive... Eric Nelson

MW 08:07 PM MitySOM-AM57X PCB Development: RE: Unconnected pins, board dimensions and hole positions

Hello.
1. Generally speaking, all of the MFIO pins are direct connects to the AM57xx CPU device and if they are unused in your design it is safe to leave them not connected. The Ball numbers are included in the table and can be cross... Michael Williamson

TC 06:51 PM MitySOM-AM57X PCB Development: Unconnected pins, board dimensions and hole positions

Posting on behalf of customer:
1.The J1 and J3 connectors of MitySOM-AM57 are described as “MFIO” for “Type”.
"If this pin is not used, can it be left unconnected?"
(Table 6, Table 7 in MitySOM-AM57_datasheet.pdf)
2.Is it okay... Thomas Catalino

06/14/2023

JC 02:46 PM MitySOM-AM57X PCB Development: RE: Design support for USB for use with AM57x SOM

Datasheet has been released Jonathan Cormier

06/09/2023

SS 04:53 PM MitySOM-AM57X PCB Development: RE: Design support for DP83640 Phy IC for use with AM57x SOM

Hi,
For testing IEEE 1588 H/W time stamp application, we included DP83640 in our circuit. Since DP83640 doesn't have 1.8V I/O level, we used Voltage level converters TXS0104E (Bidirectional, Push-pull and Open drain compatible) and SN... Sandeep Sivadas

06/07/2023

JC 01:47 PM MitySOM-AM57X PCB Development: RE: eMMC support for MitySOM AM572x

Per this e2e post, it should be okay to use 1.8V signal levels with an eMMC.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/827480/am5718-emmc-at-1-8v
The eMMC_RSTn signal can be connected to any gpio on ... Jonathan Cormier

SS 07:25 AM MitySOM-AM57X PCB Development: RE: eMMC support for MitySOM AM572x

Hi Jonathan,
We designed an eMMC circuit using *MTFC16GAPALBH-AIT*. As per the data sheet of MitySOM MMC2 signals are 1.8V level.
we follow the AM572x-IDK schematic design for designing eMMC circuit. But there an eMMC_RSTn signal is ... Sandeep Sivadas