Activity

From 06/27/2019 to 07/26/2019

JC 01:34 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal): Aviv Prital wrote:
> Hi, thanks for reply!
> ...
The dsplink sources are in the 2014 MDK. MDK_2014-01-13/sw/3rdparty/dsplink_linux_1_65_00_03
Syslink can be download here: http://downloads.ti.com/dsps/dsps_public_sw/sdo_sb/targetconte... Jonathan Cormier

AP 06:00 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal): Hi, thanks for reply!
Two follow up questions:
Concerning "you may want to look at some of the DSPlink or syslink code" where could I see this code?
Concerning "opening "/dev/mem" and using mmap()": will I be able to read/write to any... Aviv Prital

JC 03:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal): Note if your writing your own bare-metal communication you may want to look at some of the DSPlink or syslink code as you'll need to do similar things as they do.
Talked with another engineer.
> We have done a couple different thin... Jonathan Cormier
AP 02:05 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal): Thanks for the prompt reply!
I'm thinking about shared RAM that ARM user space linux driver will be able to mmap in order to write/read to DSP.
Thanks,
Aviv Aviv Prital
JC 02:01 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Change data between ARM(Linux) - DSP (bare-metal): Could you provide more information on what is suitable for your project? Jonathan Cormier
AP 01:44 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: Change data between ARM(Linux) - DSP (bare-metal): Hi,
I'd like to use MityDSPL138 kit in order to develop ARM(Linux) - DSP (bare-metal) data exchange over shared memory.
As far as I understand TI's DSPLink/SYSLINK rely on RTOS at DSP which is not suitable in my case.
Is there any ex... Aviv Prital

VP 02:57 PM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Reference Project AnalogExpansionSuite query: Hi,
I have a custom board with
-- MityDspl-138F module (with FPGA)
-- No Ethernet port
-- UART,USB,SD CARD interface
-- ADC5560 and DAC5672 is used.
we have done following steps till date.
-- I have built VM with MityDSP Cr... Vivek Ponnani
VP 10:05 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: uPP receive clock lower limitation in SDR (Single Data Rate mode): Thanks Greg for your reply and sorry for the late reply.
I will forward your response to our FPGA team. They are using reference from AnalogExpansionSuite (from Critical Link).
Initially as I mentioned, we are able to get demodula... Vivek Ponnani

MW 11:04 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Set timing constraints: Hi Davide,
You really need a constraints file for this to constrain the input timing signals properly based on the ADC datasheet specifications.
There are several (free) online courses available from Intel/Altera about writing timi... Michael Williamson
DV 09:20 AM MitySOM-5CSX Altera Cyclone V FPGA Development: Set timing constraints: Dear all,
I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I'm trying to do is to digitize an input sinusoid via the ADC and storing it in the internal FPGA RAM via a the RAM 2-POR... Davide Vaccaro

VJ 11:03 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9: Hi Wesley
Thank you for the proposed code change, that did the trick!
I think @static DRIVER_ATTR(fpga_uinput, S_IRUSR, fpga_uinput_show, fpga_uinput_store)@ creates the @driver_attr_fpga_uinput@ variable.
BR
VJ V J

WD 03:53 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9: Thanks for the log and module code.
We'd like to build this module in an attempt to recreate the issue, but the declaration of @const struct driver_attribute *driver_attr_fpga_uinput@ is not contained in the module code. Could you pro... Wesley Dahar
VJ 10:04 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9: Hi Dan, thanks for your reply.
I did a quick test where I replaced the 4.9 (RT) zImage with 4.1.22(RT) on my rocko SD card, and then my PIO interrupts worked as expected.
When using the kernel from the rocko branch (ref https://sup... V J

DV 08:21 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9: Hello,
We aren't aware of any changes or issues with the PIO interrupts. We haven't been able to recreate the issue that you are seeing here. Could you post your boot log and the section of code that you are using to initialize the gp... Daniel Vincelette
VJ 12:42 PM MitySOM-5CSX Altera Cyclone V Software Development: FPGA PIO interrupt issues with Rocko and kernel 4.9: Hi
After upgrading to Rocko and kernel 4.9 (RT) my pio interrupt routine is no longer working. My previous setup was Krogoth with kernel 4.1.22 where my pio interrupts were working fine.
When receiving an FPGA PIO interrupt now I get (... V J

Also available in: Atom

Mity CPU Platforms