Activity
From 06/13/2016 to 07/12/2016
07/12/2016
- JC 09:02 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Excellent glad you got it working.
- IS 12:16 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Johnathan,
Joy Joy, Happy Happy.
Everything is working. There were three items altogether. First was the "open drain" on the chip select. The EE added a pull up resistor and that worked). We were able to finally capture the spi si...
07/11/2016
- FW 05:06 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- I looked deeper into the error we were provoking on our bench; it turned out to be a c++ vector de-referencing error that was causing an invalid page fault. The error message posted above appears to be secondary fallout. I'm thinking tha...
- AD 09:41 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Tom,
As the Root Port, the HPS will control the reset to the PCIe. This can be an HPS GPIO, loaned pin, or FPGA I/O. A bank 8A pin is acceptable.
- Adam - TC 09:02 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- After a bit of rearranging, I've gained the use 179 (B8A_RX_T1_N/CLK7n) for the PERSTn. I believe that should work fine.
Thanks,
Tom. - TC 08:37 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Adam,
Thanks, I hadn't realised that restriction was just on CvP. As we don't need that, you say that any IO can be used.
Would HPS_GPIO44 (pin244 on the MitySOM) be usable if I set up HPS loaning for that pin so that the FPGA c... - AD 08:11 AM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: 5CSX-H6-53B-RC with PCIe Hard IP (Root)
- Hi Thomas,
The Cyclone V has a mode where it can be configured using CvP (Config via Protocol) - this configures the FPGA over the PCI Express bus interface. To use this mode, the PERSTN has only one option for the pin location. For...
07/09/2016
- Hi,
We are considering one of the MitySOM boards for use in one of the projects we are working on. I'm currently going over the pin mappings to make sure that we have enough pins.
I was reading through the design guide for the boar... - JC 06:24 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Ian St. John wrote:
> Can you confirm that the signal marked as 'reserved' just beside the SPI1_CSC1 is the SPI1_CSC0 and would that show the chip select operation from reading the flash? It seems a good inference but it is speculative ... - IS 05:56 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Hmm. I asked the EE about the diagram and he was interested in the fact that there was a pull up on the CS line. Apparently, none of our documents state that the SPI1_SCS[1] is "open drain".
We have
"am1808 tech ref (spruh82a)".pdf... - IS 12:40 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash which is on SPI1_CS0.+
Oops. Sorry, I said eeprom when I meant the 8MB flash. The JEDEC result is from FLASH, so ok. I modified the code to do the ... - MW 01:23 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- Hi Fred,
Syslink is newer than DSPlink, though in the context of the L138 it's very similar code (syslink evolved from DSPlink).
I am curious about the "sudden" appearance of the error following a power cycle on your fielded unit. ... - FW 12:11 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- The error collected above was on the bench after making some minor software changes seemingly unrelated with the code that accesses dsp-link; the one below was just found in the field. The field device was in operation for 2 months with ...
- FW 11:23 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: L138 dsplink problem - schedule while atomic bug
- I found the following on the TI site; looks like they struggled with this issue with sys-link... I'm not sure how sys-link is related to dsp-link (newer, older, ?)...
[[https://e2e.ti.com/support/embedded/tirtos/f/355/t/385081]]
07/08/2016
- I think there may be a bug in the dsplink kernel code that causes the scheduler to run after a call to spinlock. "remove_wait_queue" seems to be in atomic code, and anything that can cause a call to the scheduler is not allowed after a s...
- JC 09:33 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: SPI1 controller, access to FLASH and carrier board. NOT linux based.
- Ian St. John wrote:
> I am building and programming a custom board without Linux. Basic embedded drivers running from SPI1,CS0 (8MB NOR Flash).
> ...
The eeprom is on the i2c0 bus. I'm assuming you are talking about the SPI Nor flash...
07/07/2016
- DV 11:26 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: /sys/class/fpga-bridge directory is empty
- Thank you for letting us know about this, it was a bug that was caused by some updates to the ethernet driver, which in turn caused some changes in the dtsi. I've pushed the fix to our git repo, it converts how the reset manager was inte...
07/05/2016
- I am building and programming a custom board without Linux. Basic embedded drivers running from SPI1,CS0 (8MB NOR Flash).
CCS version 6.1.3, compiler TI 15.15.1 LTS, custom carrier board with 1808-FX-225-RC (MityARM 1808) SOM.
I can ...
06/30/2016
- AB 11:08 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?
- Malcolm,
Thanks for catching the typo, it's been updated.
With the CSEL "properly" set and the module still not operating as expected it does still appear that an RMA will still need to be done for us to dig into the issue further.... - MH 03:49 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?
- Alex,
Thank you for the reply.
I've checked the "gotchas" wiki page and the CSEL setting was the only thing not correct (and now corrected).
A correction for the Wiki is to change "page 469" to "page 459" three lines up from th... - I downloaded the latest kernel sources from the critical link repo, rebuilt the kernel and .dtb files, and loaded them on the sdcard. Everything works fine except I lost the fpga2hps, hps2fpga, and lwhps2fpga folders under the /sys/clas...
06/29/2016
- AB 10:01 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?
- Malcolm,
Dan and Adam brought this issue to my attention and I will followup concerning the RMA replacement via e-mail.
Please note that the current Development Kit Hardware Quickstart Guide (https://support.criticallink.com/redmin... - MH 05:55 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?
- I've tried both suggestions but the result is the same, I get the "CALIBRATION FAILED" message on my first board and the second board works.
Can I send the SoM back for a replacement?
Thanks,
Malcolm
06/28/2016
- MH 11:56 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?
- Dan,
I've downloaded the file you provided the link for but first ...
Adam,
I presently have CSEL[0-1] set to logic high as per the switch settings of the Critical Link dev board as it was supplied. I now have my own base board ... - AD 11:39 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?
- There is a CV errata that can cause such a failure. Please check that the CSEL[0-1] pins are set to "00" to avoid a potential HPS PLL issue.
!MSEL-CSEL-BSEL.png!
Thanks,
Adam - DV 11:13 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Why do I get a "CALIBRATION FAILED" error during boot?
- Hello Malcolm,
I know you said that your current SD card works for one of your SOMs but would you mind trying our prebuilt 5CSX-H6-4YA SD card image just to double check that the SOM that fails RAM calibration still acts the same? It ... - I have been using the same module for the last two weeks and today it has started giving the "CALIBRATION FAILED" error message as listed on the Wiki's ARM Software FAQs page.
06/24/2016
- DV 01:10 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse
- Hi Sam,
I've been able to recreate what you're seeing. It looks like the devicetree generated through yocto is named socfpga_mitysom5cse_devkit.dtb and what uboot is looking for on the SD image that ships with the 5CSE devkit is socfp... - SS 06:41 AM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Development Kit 2.5V VIO, change to 3.0 or 3.3
- Thank you Alex, that's exactly what I wanted to know. I understand your point about the warranty, and proceeding carefully.
Best,
Steve
06/23/2016
- AB 04:47 PM MitySOM-5CSX Altera Cyclone V PCB Development: RE: Development Kit 2.5V VIO, change to 3.0 or 3.3
- Stephen,
Thanks for reaching out to us about this question.
Please note that making any modification to the carrier board, such as this, will void any warranty for both the carrier board and any module used in that board.
Unfor... - It looks like banks 3B, 4A, and 8A have their I/O voltage tied to a 2.5V supply on the development kit.
If I want to interface with 3.0 or 3.3V logic via the HSMC cards, can I safely modify the feedback resistors on U601 to change the... - DV 12:32 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse
- Hi Sam,
I'm currently re-running the yocto build here to see if I can recreate the issue you are seeing. I will update when I have a result.
Dan - SA 11:36 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse
- Hi Alex,
I selected the 5cse for the build, not the 5csx. I have done this full build no fewer than 3 times with what I believe to be the correct settings, and had consistently non-functional results.
I will try the updated instru... - AB 11:17 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Building BSP for 5cse
- Sam,
I believe that the issue you ran into if following the Yocto wiki steps is that you may have selected the "mitysom-5csx" machine type as shown in the instructions. In your specific case you would actually want to select the "mity...
06/22/2016
- I am trying to follow your documentation for using Yocto to build an image for the 5CSE on the dev board carrier, and having nothing but trouble.
I have followed the exact instructions on your support page, and successfully compiled a... - PB 04:13 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: kernel 3.2 - tcpip stack latency
- Hi Greg,
Than you for your feedback.
Indeed, flag CONFIG_PREEMPT is set in kernel config. As far as we can see, there is no issue on the thread itself.
We use VLAN tag to route the traffic specifically from the devices to our c...
06/21/2016
- GG 01:30 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: kernel 3.2 - tcpip stack latency
- Hi Patrice,
Since you are using SCHED_RR I am assuming you are using CONFIG_PREEMPT in your kernel config, correct?
Does your design have any sort of network traffic shaping or advanced traffic control in place? I do not think an... - Hello,
We've built an application receiving messages from two devices at a rate of 1 message of 1440 bytes every 10 ms in a thread schedule in SCHED_RR priority 70. This is the higher priority user thread in the system.
A network tra... - MS 03:45 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's
- Hi Alex,
Still a few misnumbered things in the above post.
Anyway, removing the switches from the DTS means that the GPIOs don't go to high impedance any more, and whatever I set them to in uBoot persists, but I still can't control...
06/20/2016
- AB 01:15 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: HDMI Output and Quartus Versions
- Steve,
We have successfully rebuilt the "HDMI example":https://support.criticallink.com/redmine/projects/5csxbase/wiki/HDMI_Output using Quartus 14.1 however you will require a license to support the VIP Suite (Video and Image Process... - Hi,
I noticed that the HDMI Output example you've posted was done in Quartus 15.1 but the VM with the toolchain installed is still on Quartus 14.x. What would you recommend for someone deriving a project from the HDMI example? Shoul... - AB 01:10 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's
- Maetthew,
Good catch. Apparently when I did the mapping I started off by one. We have updated the post above to have the correct mapping and also the associated wiki page (https://support.criticallink.com/redmine/projects/mityarm-5cs/... - MS 02:09 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's
- I have noticed that in the DTS the switches are now on the GPIOs that I want to use:
http://support.criticallink.com/gitweb/?p=linux-socfpga.git;a=blob;f=arch/arm/boot/dts/socfpga_mitysom5csx_devkit.dts;hb=refs/heads/socfpga-3.16
I s...
06/19/2016
- MS 11:26 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: How to add aditional HPS GPIO's
- I'm having some issues setting GPIO37, 40 and 41 from within Linux.
Firstly, in the instructions above, you mention that GPIO29 to GPIO57 are mapped to gpio198 to gpio226, but then go on to say that GPIO49 corresponds to gpio217. Shou...
06/17/2016
- FW 08:25 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Flashing a new kernel to NOR from Linux rather than u-boot
- Here are the results from my board/MDK:
06/16/2016
- JC 05:43 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Flashing a new kernel to NOR from Linux rather than u-boot
- Alternatively it may be possible for you to build the kernel features as modules and insert them in the live system. Would like to see the output of the commands mentioned above first.
- JC 05:39 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Flashing a new kernel to NOR from Linux rather than u-boot
- Fred,
Do you have /dev/mtdblock* devices? My kernel boot args have this "root=/dev/mtdblock0", so my assumption is that you will need to have the mtdblocks enabled inorder to boot from nand.
If you do have the mtdblock devices it ... - We use opkg to push updates to our products that are installed in the field. We now need a way to update the kernel, which is saved in NOR on the MityDSP-l138 som. A search of the CL wiki shows:
@flashcp -v uImage /dev/mtd7@
We hav...
06/15/2016
- JC 05:14 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to configure the GPIOs as outputs?
- Do note that the custom baseboard instructions were written for the 335x family. So some things will be slightly different. For example:
Instead of @arch/arm/mach-omap2/@ you should look in @arch/arm/mach-davinci@ for the board (boar... - BD 04:14 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: How to configure the GPIOs as outputs?
- Héctor,
Please check the last section of this page for information on how to review and set the pinmux for the development board:
https://support.criticallink.com/redmine/projects/armc8-platforms/wiki/Creating_a_custom_baseboard
... - Hi, it's me again,
I'm knowing the Profibus Development Kit (and embedded systems) and for that I'm trying to do simple codes in C++ in Eclipse,
I was checking the datasheet about the connector pin assignments and the signals names... - HB 11:00 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- Now it's working, thanks a lot Jonathan!
- JC 10:02 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- Hector Bojorquez wrote:
> > This is a error is normal and doesn't hurt anything.
> ...
These settings only affect u-boot. You need to configure the ip settings after booting into linux.
> U-Boot > print bootargs
> ...
https://suppor... - HB 09:55 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- > This is a error is normal and doesn't hurt anything.
*
So, the reflashing process went well?*
> ...
I tried with this [[Setting_a_Static_IP_Address#NFS-Mounted-File-System]]
@U-Boot > print bootargs
bootargs=mem=96M console=tt... - JC 08:38 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- Hector Bojorquez wrote:
> >There shouldn't be a space in the console arg. "console=ttyS1,115200n8"
> ...
This is a error is normal and doesn't hurt anything.
>
> ...
If you don't have a dhcp server then you will need to set your ip...
06/14/2016
- HB 05:45 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- >There shouldn't be a space in the console arg. "console=ttyS1,115200n8"
> ...
sorry about that, I was watching from the other PC and typing in the one with Network connection for making the post, but in the bootlog is OK,
>There sh... - JC 03:35 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- Hector Bojorquez wrote:
> Hi Jonathan,
> ...
There shouldn't be a space in the console arg. "console=ttyS1,115200n8"
Also root should have an '=' not a '-'.
From attachment:UpdatingDevKitMDK.txt
> U-Boot > setenv bootcmd "runflas... - HB 02:56 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- Hi Jonathan,
I made the changes, and yes the problem continues the same, I checked the bootargs and this was the result:
@U-Boot > print bootargs
bootargs=mem=96M console=ttyS1, 115200n8 root-/dev/mtdblock0 rw rootwait@
>If t... - JC 01:20 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- Thanks for all the logs, definitely helpful. The kernel panic indicates that it failed to find the filesystem. See below.
- HB 12:50 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Problems with the first time configuration
- Hi,
I followed the steps in the [[Reprogramming_a_Dead_Board]] guide and I got access to the u-boot prompt again, so I tried again with the [[Updating_devkit_to_latest_MDK]] tutorial
I left attached the bootlog, after that I tried ... - BD 05:15 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Specifics on reserving DDR for PRU/ARM shared use
- Regarding your specific questions, yes, you could use memmap to set aside a particular chunk of memory. Where you set it up depends on the amount of memory in your module and I expect you could access it from base SDRAM address @0x8000_0...
- BD 05:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Specifics on reserving DDR for PRU/ARM shared use
- Hi Andrew,
I recommend you review the TI-provided documentation and examples for the PRU available here:
<https://github.com/beagleboard/am335x_pru_package>
This documentation is compatible with the PRU Module for the 3.2 kernel...
06/13/2016
- BD 05:14 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: JFFS2 "scheduling while atomic" problem with L138 running linux kernel 3.2
- Sorry I missed that Fred.
You can just make the change (swapping two lines) yourself for testing, or you can apply the commit via Jon's instruction.
If that fixes your problem, we can push it to our main branch.
- JC 05:12 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: JFFS2 "scheduling while atomic" problem with L138 running linux kernel 3.2
- Note we can list any other jffs patches that is in the linux-3.2.y branch that isn't in ours by doing the following:
- JC 05:07 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: JFFS2 "scheduling while atomic" problem with L138 running linux kernel 3.2
- The patch was included in the 3.2.18 kernel release. You can cherry-pick the patch from there to verify it fixes your issue.
- JC 04:56 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: JFFS2 "scheduling while atomic" problem with L138 running linux kernel 3.2
- Looks like someone already did the backport of the fix. The patch is very straight forward.
https://github.com/Angstrom-distribution/meta-ti/blob/master/recipes-kernel/linux/linux-ti33x-psp-3.2/3.2.18/0027-jffs2-Fix-lock-acquisition-or... - FW 04:28 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: JFFS2 "scheduling while atomic" problem with L138 running linux kernel 3.2
- Ah, yes, so this is indeed the problem; the code you show above is _before_ the fix. The issue is mutex_lock cannot follow spin_lock. Spin_lock places the kernel into atomic mode; during this mode, the processor must not call scheduler, ...
- BD 02:48 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: JFFS2 "scheduling while atomic" problem with L138 running linux kernel 3.2
- Fred,
The current MityDSP-L138 kernel (Branch: mitydsp-linux-v3.2) has the following code in @fs/jffs2/gc.c@: - I have been getting a lot of "scheduling while atomic" messages seemingly centered around JFFS2:
@Jun 12 12:08:37 ultrasonic kernel: BUG: scheduling while atomic: flash-writer/2221/0x00000002
Jun 12 12:08:37 ultrasonic kernel: Module...