Activity

From 10/22/2014 to 11/20/2014

GG 05:16 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA configuration via u-Boot problem: You can also use the promgen command to generate a bin file from a bit:
promgen -w -p bin -u 0 filename.bit -o filename.bin
\Greg Gregory Gluszek
02:35 PM MitySOM-5CSX Altera Cyclone V Software Development: RE: Kernel Driver: Hi
I compiled the kernel driver with the Linux kernel in the instruction here (https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Linux_Kernel).
Now I'm getting this error:
fpga_uinput: version magic '3.12.0-g456... Anonymous
MW 07:29 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: RE: PlanAhead issue: For ISE (and I think ISE / PlanAhead are still the tools for Spartan 6, as the Vivado tools are for 7 series and higher), if you analyze your design with commercial temp and keep the non-commercial parts within their rated voltages and t... Michael Williamson
OM 03:21 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: PlanAhead issue: Hi,
Why at creation of the project in PlanAhead 14.7 for the chip xc6slx45csg324-3 it is not possible to specify Temp Grade I (only C)? In fact according to the specification on L138-FI-236-RL-ND it works in a range-40°C ~ 70°C.
Best... Oleh Mela

SK 07:51 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: FPGA configuration via u-Boot problem: Hey,
I solved the problem.
It's important that the FPGA config file <fpga>.bin file was created correctly.
By using Xilinx Impact I selected the following options in the "Create PROM file" dialog:
1. Generic Parallel PROM
2. ... Stefan Krassin
SK 07:30 AM MityDSP-L138 (ARM9 Based Platforms) Software Development: FPGA configuration via u-Boot problem: Hi all,
I have a problem with the configuration of the FPGA and booting linux.
I followed the instructions from CL "Using u-Boot to load the FPGA".
If I run the boot command "bootcmd=sf probe 0; sf read 0xc0700000 0x100000 0x280... Stefan Krassin

04:26 PM MitySOM-5CSX Altera Cyclone V Software Development: Kernel Driver: Hi,
I'm trying to lad a kernel driver by following example on this page https://github.com/zhemao/interrupt_example
However, after run "insmod fpga\_uinput.ko" I get the following error.
fpga_uinput: version magic '3.9.0-00161-g... Anonymous

02:38 PM MitySOM-5CSX Altera Cyclone V Software Development: SOCKIT GSRD: Hi,
For my project, I'm trying to use precompiled Linux libraries with Sockit as seen in this link "http://rocketboards.org/foswiki/Documentation/ArrowSoCKITEvaluationBoardLinuxGettingStarted#Creating_an_SD_Card_using_a_Windows_Host"
... Anonymous

DG 01:52 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes: Hi Mary,
As you suspected in your original post, it is likely that when you are calling fwrite, in some cases the write cache is full and is causing full flush down to storage (NAND). In this case it will take longer than just writing... Dominic Giambo
MF 01:04 PM MityDSP-L138 (ARM9 Based Platforms) Software Development: RE: Real time SATA writes: After further testing and setting optimization, I have narrowed down the delay:
The call to fwrite() normally takes about 2.5 msec, but occasionally (on the order of minutes) this call can take 20 msec, 40 msec, 150 msec, or even 300... Mary Frantz

DV 02:22 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA: Hi Jack,
We don't have any explicit examples of this but you will want to look into the userspace I/O driver. This should allow you to map in the FPGA interrrupts to a /dev/uio device.
I did a bit of searching and this looks like a... Daniel Vincelette

01:40 PM MitySOM-5CSX Altera Cyclone V FPGA Development: RE: Modular SGDMA: Hi Dan,
The issue seems to be with the polling. I brought out the empty signal to an oscilloscope and found that it is on, but for some reason I'm not reading that on the software side.
I think it's better to switch to interrupt to... Anonymous

OM 10:44 AM MityDSP-L138 (ARM9 Based Platforms) FPGA Development: Clock for FPGA: Hi.
I'm using MityDSP-L138F Board. As will ensure that the generated clock signal to FPGA?
Thanks Oleh Mela

CK 10:58 AM MitySOM-5CSX Altera Cyclone V Software Development: RE: Performance problem with baremetal code: In the meanwhile and after an ARM Cortex training I've found the root cause of the problem:
For enabling the caches, you have also to initialize the MMU, e.g. with the attached version of performance.c. Nevertheless the baremetal code... Christian Kempter

JC 11:48 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications: Theres a 24MHz crystal between XTALOUT and XTALIN on the ARM. Its frequency tolerance at 25C is +/- 25ppm.
Note these numbers are based on a 3359-GX-226-RL RevD. Jonathan Cormier
CL 11:42 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications: Great, thank you for the information. Is it a similar specification for the other oscillator on the board, connected to the ARM? Chris Leon
JC 11:31 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RE: RTC Crystal Specifications: For the 32khz crystal attached between the OSC32KOUT and OSC32KIN pins, according to its datasheet, the frequency tolerance at 25C is +-10ppm. Jonathan Cormier
CL 10:56 AM MitySOM-335x (ARM Cortex-A8 Based Products) PCB Development: RTC Crystal Specifications: What are the ppm drift specifications for the TPS65910 RTC crystal? Chris Leon

AB 04:10 PM MitySOM-335x (ARM Cortex-A8 Based Products) Software Development: RE: Communicating with an 8-bit parallel interface (GPIO, SPI or GPMC): Updated question(s) from the customer:
I've been looking into using GPMC. The Technical Reference Manual for the AM335x says that GPMC has a 512MB address space. Since the module I have has a 512MB NAND flash on GPMC, configuring anot... Alexander Block

MW 10:41 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: L138 SOM LEDs: Sorry,
On Non-FPGA modules:
D1 is connected to R16 (GP6_12) of the OMAP-L138.
D2 is connected to R17 (GP6_13) of the OMAP-L138.
-Mike
Michael Williamson
AK 10:05 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: L138 SOM LEDs: Hi Mike,
The SOM we are using is the non-FPGA version. What do D1 and D2 connect to?
Thanks,
Anton Anton Kitai
MW 07:22 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: L138 SOM LEDs: D1 is connected to the FPGA_DONE pin on the FPGA configuration block.
D2 is connected to P15 of the FPGA IO_L74P_AWAKE_1
D3 is connected to P16 of the FPGA IO_L74N_DOUT_BUSY_1
-Mike
Michael Williamson
AK 10:03 AM MityDSP-L138 (ARM9 Based Platforms) PCB Development: RE: MityDSP-L138 Boot Problem: This issue has been resolved - we had left an uterminated SPI1_CLK signal trace on our base board at an unpopulated device.
Anton Anton Kitai

AK 03:13 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: L138 SOM LEDs: Please can you provide information for D1 and D2 LEDs on the L138-FX-225-RC module. What are they connected to?
Thanks,
Anton Anton Kitai
AK 02:05 PM MityDSP-L138 (ARM9 Based Platforms) PCB Development: MityDSP-L138 Boot Problem: We are using the L138-FX-225-RC on a new custom baseboard and are having trouble with boot:
- no UART activity in normal SPI boot
- UART boot mode sends "BOOTME"
We attempted to erase and flash the bootloader using the WinCE boot pa... Anton Kitai

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