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From 01/09/2026 to 02/07/2026

DV 10:17 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
It looks like you have spelling mistake in your command, it should be the following: Daniel Vincelette
XS 09:11 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Dan,
I meet an issue at step 4 configure and build U-boot and the SPL.
$ make socfpga_nitysom5cs_defconfig
Makefile:40: *** missing separator. Stop
what can I do?
BR,
Xiang Xiang Shuai

DV 09:42 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
The fpga2sdram_handoff vairable will be set from the quartus project so you don't need to manually change it. Here are our build instructions for the preloader and u-boot: https://support.criticallink.com/redmine/projects/mi... Daniel Vincelette
XS 09:04 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Dan,
I download uboot-socfpga.tar.gz, but I don't know how to update `fpga2sdram_handoff` variable in u-boot. Could you give me a detail instruction ? Thanks!
BR,
Xiang Xiang Shuai

XS 04:42 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Thanks Dan, I tried change resigster 0xFFC25080 from 0x00000000 to 0x000003FF, but still timeout. I will update u-boot to try again. Xiang Shuai
DV 04:11 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: A colleague just informed me that even if you set that variable to enable the bridges, it may still not work because the preloader also enables the bridges as part of configuring the HPS I/Os. Because of this, the correct and supported p... Daniel Vincelette
DV 03:58 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
You would need to update the `fpga2sdram_handoff` variable in u-boot to enable the ports that you would like. Here is the HPS doc on the FPGA port controller register map: https://www.intel.com/content/www/us/en/programmable... Daniel Vincelette
XS 02:36 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Dan,
Thanks for your information, instead of rebuild preload and u-boot, do you have any command that can do release these bridges out of reset? Now, I can use Putty connect system by SSH.
BR,
Xiang Xiang Shuai

DV 09:59 PM FPGA Development: RE: JTAG_avalon_master access HPS DDR timeout: Hi Xiang,
When you enabled the FPGA to HPS SDRAM bridge did you also rebuild your preloader and u-boot? This is needed because the HPS is the one that takes these bridges out of reset.
Best regards,
Dan Daniel Vincelette
XS 09:28 PM FPGA Development: JTAG_avalon_master access HPS DDR timeout: Hi,
Using MitySOM_5CSX, I added FPGA to HPS SDRAM interface avalon-mm read-only, and try to using jtag_avalon_master to read out the data from HPS DDR, but always timeout. Need a bridge or something worng?

clipboard-20260202... Xiang Shuai

MF 08:37 PM FPGA Development: RE: MitySOM-5CSX (5CSX-H6-42A-RI) stops at “Deasserting all peripheral resets” — request for guidance: The RMA on this thread has been handled and completed.
For anyone looking for resolution to the question about the encrypted FPGA bitstream, see the following forum post: https://support.criticallink.com/redmine/boards/47/topics/7107 Mike Fiorenza

SG 04:14 PM FPGA Development: RE: Building the MitySOM-5CSX: Hi John,
Glad you were able to work through the stuff I described and get things working, you're welcome!
Yes, great observation. Lines 549-562 are the I/O available on the partial header, while the rest are available on the full h... Seth Graber
JI 12:28 PM FPGA Development: RE: Building the MitySOM-5CSX: Hi Seth,
I found all the stuff that you described below and have started to study the .vhd file. Thanks. I also got bit 30 to work as described.
That said, it appears (from the .vhd file, lines 549-562) that those I/Os are only avai... John Iannuzzi

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