Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

02/06/2025

DV 02:27 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
It looks like you have a signaltap in your design, which can make it hard to meet timing. I recommend that you remove it and try a build again. If that doesn't work then you'll need to use Timequest 's Worst Failing paths report t... Daniel Vincelette

BK 02:14 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
I am facing an issue with new Timing Error in my Project which that generated rbf file, it was not pinging and as well as the source System continuously sending ARP messages only without sending the Ping data ,but in two systems E... Bhardwaj Kotha

01/23/2025

TI 08:40 PM Software Development: RE: MTU increase Issue

What Dan showed you will start your application in the console... if your application exits (or you kill it with ctrl-c) you will be dropped to the command line, where you can restart your application or do other things. Tim Iskander

DV 06:55 PM Software Development: RE: MTU increase Issue

Hello,
As Tim said an application launched through cron won't have access to standard in and out. What you could do is have getty(the login manager) autologin as root and use a .profile config file to launch your application.
Here ... Daniel Vincelette

BK 03:17 PM Software Development: RE: MTU increase Issue

Hi,
I am currently working with the MitySOM Cyclone V device, which has only a single UART port. During boot-up, the boot logs are coming through this UART port. Once the system finishes booting, it prompts for a login. I am manually ... Bhardwaj Kotha