Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

08/01/2024

BK 12:52 PM FPGA Development: RE: MitySOM-5csx custom board PL fabric ethernet access

Hi,
Actually that timing issues were resolved and ping performance also well as of now without packet loss. And now I am working fine with RGMII splitter connected to the HPS EMAC of latency 2 microseconds in my setup, I want to under... Bhardwaj Kotha

07/31/2024

TI 03:39 PM Software Development: RE: Receive and send data using vlan tag

Bhardwaj
There should be no devicetree changes necessary to use the VLAN feature of the Ethernet.
You verified that the 8021q module is loaded.
You should be able to create a VLAN interface and configure it from the shell and then add... Tim Iskander

BK 05:55 AM Software Development: Receive and send data using vlan tag

Hi,
I am working on ethernet using vlan. I had used the ip command to create the vlan after that some data sent from another PC having vlan and run receive code on board to receive data but we didn't get any data. when we try these e... Bhardwaj Kotha

07/25/2024

GG 07:47 PM Software Development: RE: how to access gpio using pio ip core in c code

Hello,
I would look at the avalon memory mapped slave address in your signal tap. It's possible the hps is requesting a read from a different address for one of those two cycles. It's also possible two reads are queued up back to bac... Gregory Gluszek

07/24/2024

BK 07:11 AM Software Development: RE: how to access gpio using pio ip core in c code

Hi,
Yes, I am verified in Signal Tap only. and as off now like, we are able to do read and write HPS to FPGA using LW_AVALON_MM interface. In case of read from HPS, avalon_slave_read signal is being high for two clock cycles. Where as... Bhardwaj Kotha

07/23/2024

GG 04:12 PM Software Development: RE: how to access gpio using pio ip core in c code

It looks like you posted a couple different versions of your C code. Which one are you running and what does the output look like? How are you verifying the FPGA is receiving data from the HPS? Are you using signal tap?
Thanks,
Greg Gregory Gluszek

07/22/2024

BK 03:16 PM Software Development: RE: how to access gpio using pio ip core in c code

Hi,
In my implementation, the Avalon Memory Mapped interface automatically assigned a base address in platform designer with that address only I successfully sent an 32bit incremental data from the HPS to the FPGA and received it corr... Bhardwaj Kotha