Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

07/03/2019

MW 11:04 AM FPGA Development: RE: Set timing constraints

Hi Davide,
You really need a constraints file for this to constrain the input timing signals properly based on the ADC datasheet specifications.
There are several (free) online courses available from Intel/Altera about writing timi... Michael Williamson

DV 09:20 AM FPGA Development: Set timing constraints

Dear all,
I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I'm trying to do is to digitize an input sinusoid via the ADC and storing it in the internal FPGA RAM via a the RAM 2-POR... Davide Vaccaro

07/01/2019

VJ 11:03 AM Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9

Hi Wesley
Thank you for the proposed code change, that did the trick!
I think @static DRIVER_ATTR(fpga_uinput, S_IRUSR, fpga_uinput_show, fpga_uinput_store)@ creates the @driver_attr_fpga_uinput@ variable.
BR
VJ V J