Activity
From 06/28/2019 to 07/27/2019
07/03/2019
- MW 11:04 AM FPGA Development: RE: Set timing constraints
- Hi Davide,
You really need a constraints file for this to constrain the input timing signals properly based on the ADC datasheet specifications.
There are several (free) online courses available from Intel/Altera about writing timi... - Dear all,
I have a MitySOM 5CSX-H6-4YA with a Cyclone V SoC installed on a custom board with ADCs and DACs. What I'm trying to do is to digitize an input sinusoid via the ADC and storing it in the internal FPGA RAM via a the RAM 2-POR...
07/01/2019
- VJ 11:03 AM Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9
- Hi Wesley
Thank you for the proposed code change, that did the trick!
I think @static DRIVER_ATTR(fpga_uinput, S_IRUSR, fpga_uinput_show, fpga_uinput_store)@ creates the @driver_attr_fpga_uinput@ variable.
BR
VJ
06/28/2019
- WD 03:53 PM Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9
- Thanks for the log and module code.
We'd like to build this module in an attempt to recreate the issue, but the declaration of @const struct driver_attribute *driver_attr_fpga_uinput@ is not contained in the module code. Could you pro... - VJ 10:04 AM Software Development: RE: FPGA PIO interrupt issues with Rocko and kernel 4.9
- Hi Dan, thanks for your reply.
I did a quick test where I replaced the 4.9 (RT) zImage with 4.1.22(RT) on my rocko SD card, and then my PIO interrupts worked as expected.
When using the kernel from the rocko branch (ref https://sup...