Mity CPU Platforms » MitySOM-5CSX Altera Cyclone V

03/27/2019

DV 09:53 AM FPGA Development: RE: Problem when programming FPGA from HPS

I attach the simple block diagram-based Quartus project that takes in input a 100 MHz differential clock and outputs a single-ended 25 MHz clock. It makes not use of Qsys and it isn't changing the HPS subsystem, but nonetheless I'm facin... Davide Vaccaro

03/26/2019

MW 05:23 PM FPGA Development: RE: Problem when programming FPGA from HPS

Can attach a copy of your reference project? Is it based off of the one on our support site?
-Mike Michael Williamson

DV 04:55 PM FPGA Development: RE: Problem when programming FPGA from HPS

So, I tried all the methods listed in https://rocketboards.org/foswiki/view/Documentation/GSRD131ProgrammingFPGA, but none is working. In particular:
* I'm not successful in configuring the FPGA from the Preloader because I'm not bein... Davide Vaccaro