Activity
From 03/06/2019 to 04/04/2019
03/27/2019
- DV 09:53 AM FPGA Development: RE: Problem when programming FPGA from HPS
- I attach the simple block diagram-based Quartus project that takes in input a 100 MHz differential clock and outputs a single-ended 25 MHz clock. It makes not use of Qsys and it isn't changing the HPS subsystem, but nonetheless I'm facin...
03/26/2019
- MW 05:23 PM FPGA Development: RE: Problem when programming FPGA from HPS
- Can attach a copy of your reference project? Is it based off of the one on our support site?
-Mike - DV 04:55 PM FPGA Development: RE: Problem when programming FPGA from HPS
- So, I tried all the methods listed in https://rocketboards.org/foswiki/view/Documentation/GSRD131ProgrammingFPGA, but none is working. In particular:
* I'm not successful in configuring the FPGA from the Preloader because I'm not bein...
03/25/2019
- DV 03:11 PM FPGA Development: RE: Problem when programming FPGA from HPS
- Hi Mike,
in the "final" Quartus program I will indeed need to change the configurations you mentioned, but for a start I decided to use a very simple Quartus project, which does not touch the HPS subsystem (a basic bdf that turns a di...
03/20/2019
- I've got a SOM with 2 QSPIs. I'd like to be able to access both in Linux. Does anyone have an example of a .dts file that generates a .dtb which allows Linux to access both QSPI devices?
03/19/2019
- MW 03:40 PM FPGA Development: RE: Problem when programming FPGA from HPS
- Hi Davide,
Are you enabling or changing the configuration of the FPGA to SDRAM (fpga2sdram) or HPS AXI crossbars in the HPS configuration or enabling additional peripherals in the HPS subsystem?
If you are, then you will need to ge... - Hi everyone,
I looked at previous posts but the solutions outlined does not seem to work in my case, so I'm writing as well in hope to solve the problem I'm experiencing.
I am using a Critical Link Development Kit with a MitySOM-5C...