Activity
From 01/08/2019 to 02/06/2019
02/04/2019
- I've noticed the u-boot you've provided on your git server is the socfpga_v2013.01.01 branch. I'm having some problems with fatwrite in u-boot. When I run it in the debugger I see everything go south when the set_cluster function tries t...
01/17/2019
- VJ 09:32 AM Software Development: RE: Second PHY MDIO interface
- Dan, thanks for your feedback. Lesson learned: Always rebuild the preloader.
That fixed my MDIO issue.
Regarding the PHY mode: I am using a 100Mb PHY with RMII interface, and I don’t think my original scheme with the Splitter and RGMI...
01/14/2019
- SA 05:55 PM Software Development: RE: RGMII pad skew on KSZ9031
- Thanks for the reply Mike. I'll talk to the software team and see if VxWorks resets the PHY. If not, then we will try the script route. If it does, we'll talk more later.
- MW 11:22 AM Software Development: RE: RGMII pad skew on KSZ9031
- Are you using uBoot to boot VxWorks?
I don't think there is enough space in the preloader to include the MDIO driver code and configure the RGMII, but I haven't ever tried that.
Updating the uBoot code should be pretty simple to ad... - DV 04:10 PM Software Development: RE: Second PHY MDIO interface
- Hi Vidar,
It looks like you are using Critical Link's 4.9 branch, is that correct?
Have you rebuilt and updated your preloader since enabling EMAC0? Seeing as you saw TX data out of the MDIO interface I'm assuming you have but I'm ...
Hi
I have added a second PHY to my board and connected it through the FPGA IO. I am using HPS EMAC0 and have added the emac splitter and the gmii_to_rgmii adapter in QSYS.
My problem is the MDIO interface. Connecting SignalTap to the...
01/13/2019
- We've got a custom board which is based on CriticalLink's baseboard. The PHY is the 9031. Try as we might to maintain the integrity of the RGMII signals on the PCB it seems the only way to get Gigabit working is to tweak the pad skew reg...