Activity
From 07/01/2017 to 07/30/2017
07/20/2017
- MW 06:09 PM Software Development: RE: I2C Slave Communication Hanging
- So I didn't respond right away as you are using verilog and I am more of a VHDL guy, but there is an open drain primitive called OPNDRN.
You can see an example of it inferred in VHDL here (bottom of file) for I2C routing like you are ... - JP 05:43 PM Software Development: RE: I2C Slave Communication Hanging
- We appear to have finally discovered the root cause of our issue. We actually had a self-inflicted bug where the SCL line on this one port was defined as "output" rather than "inout". Thus, we didn't really have the "open drain" we thoug...
07/19/2017
- JK 07:39 PM Software Development: RE: I2C Slave Communication Hanging
- Dan,
I've attached 2 scope shots between the Aardvark as master and the ST1633 as slave:
1. A single byte write with a value of 0x01
2. A subsequent single byte read, which we expect to return 0x04 (and does, in this trace)
This ... - JK 03:42 PM Software Development: RE: I2C Slave Communication Hanging
- Dan,
We'll be conducting investigations this afternoon with both the Linux I2C kernel driver and a bit-bang I2C user-space module we just finished writing. As a part of those investigations, we'll send along a read request capture bet... - DV 03:45 AM Software Development: RE: I2C Slave Communication Hanging
- Jared,
To me it looks like the scope capture you've shown should be correct and as you've said there shouldn't be a stop condition between the first and second byte, which is why the clock stays low. Though the second byte isn't ack'e...
07/18/2017
- JK 07:56 PM Software Development: RE: I2C Slave Communication Hanging
- Some additional context / correction:
I2C2 and I2C3 are both configured the same way. If you replace "3" with "2" in the above example, and replace "DVI" with "TFT" (related to our ST1633 touch controller), the result is the I2C2 setu... - CS 07:33 PM Software Development: RE: I2C Slave Communication Hanging
- All,
This is the open drain primitive we are using for the I2C interfaces:
wire w_i2c3_scl_oe, w_i2c3_scl, w_i2c3_sda_oe, w_i2c3_sda;
assign DVI_SCL = (w_i2c3_scl_oe) ? 1'b0 : 1'bz;
assign DVI_SDA = (w_i2c3_sda_oe) ? 1'b0 : 1'b... - MW 05:09 PM Software Development: RE: I2C Slave Communication Hanging
- Are you using the open drain primitive in the top level of the FPGA project?
-Mike
- JK 05:00 PM Software Development: RE: I2C Slave Communication Hanging
- I've attached the driver source/header. I'm waiting to hear from the touch controller vendor whether I can share the protocol description.
- JK 04:50 PM Software Development: RE: I2C Slave Communication Hanging
- We are using I2C2 routed through the FPGA fabric (see image "I2C2_Connector.PNG"). It does have pullups to the best of my knowledge (see image "I2C2_Pullups.PNG").
Though we initially tried to communicate via user space, the vendor in... - MW 04:32 PM Software Development: RE: I2C Slave Communication Hanging
- Also, Can you share a snippet of the user space code you are using to issue the read request?
Thanks.
-Mike
- MW 04:15 PM Software Development: RE: I2C Slave Communication Hanging
- Which I2C bus are you using? An HPS peripheral connected directly to HPS pins or routed via FPGA fabric?
This almost looks like there is no pull-up on the bus...
-Mike
- We're experiencing a problem with I2C communications with a slave on address 0x55 on a MitySOM-5CSX, shown in the attached image (scope_3.png).
In the image, *a read is attempted, with the first byte NACK'd by the slave, and an invali...
07/13/2017
- HB 03:29 PM FPGA Development: RE: I2C Controller
- Thank you, this was resolved, turned out to be a problem with our build scripts.
07/12/2017
- TI 12:06 PM FPGA Development: RE: I2C Controller
- Harrison
Whenever you change anything to do with HPS pin assignments, you will need to rebuild the preloader and update it on the boot media (SD card or ROM)
https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Building...
07/11/2017
- Hello,
Unsure whether to post this under the software or FPGA topic.
We are transitioning from a mostly working system developed on the Mitysom5CSX Devkit to a custom carrier board design (Cyclone V, 5CSX-H6-4YA-RC). In the previou...
07/04/2017
- TI 03:13 PM Software Development: RE: Accessing NOR flash from Linux on 5CSX
- We have a wiki page relating to using the quad spi NOR [primarily centered around booting from NOR]
(https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Utilizing_QSPI_NOR_Memory).
The bulk of it is standard linux mtd s... - BK 08:10 AM Software Development: RE: Accessing NOR flash from Linux on 5CSX
- Thanks Tim, that's good news.
Is there any specific doc. for the 5CSZ build? e.g. driver name, build instructions, code location, etc. Any examples kicking about? Do you know if anybody has tried this on the 5CSX?
Kind regards...
07/03/2017
- TI 05:22 PM Software Development: RE: Accessing NOR flash from Linux on 5CSX
- Bruce
Linux has excellent support for NOR flash devices using the mtd subsytem
http://www.linux-mtd.infradead.org/
You can read/write the device (or partition on the device) as a block or install a filesystem (such as jffs or ubifs) o... - Our project is currently in the design phase and we are considering using a small amount of NOR flash to read and write some information.
The question is whether there are built in Linux drivers to do this?
We only have a small amo...